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Wolfgang Ecker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wolfgang Ecker, Sabine März
    System-Level Specification and Design Using VHDL: A Case Study. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:505-522 [Conf]
  2. Matthias Bauer, Wolfgang Ecker
    Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:774-779 [Conf]
  3. Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker
    Re-use-centric architecture for a fully accelerated testbench environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:372-375 [Conf]
  4. Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi
    Platform-Based Testbench Generation. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11038-11045 [Conf]
  5. Michael Mrva, Mike Heuchling, Wolfgang Ecker
    The Shall-Prototype-Test Development model. [Citation Graph (0, 0)][DBLP]
    ECBS, 1997, pp:385-391 [Conf]
  6. Matthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn
    A Method for Accelerating Test Environments. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1477-1480 [Conf]
  7. Wolfgang Ecker, Lothar Schrader
    Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:313- [Conf]
  8. Wolfgang Ecker, M. Hofmeister
    State look ahead technique for cycle optimization of interacting finite state Moore machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:392-397 [Conf]
  9. Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer
    An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:187- [Conf]
  10. Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi
    Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    ISORC, 2004, pp:129-135 [Conf]
  11. Martin Zambaldi, Wolfgang Ecker
    How to Bridge the Gap Between Simulationand Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1091-1099 [Conf]
  12. Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer
    A Layered Adaptive Verification Platform for Simulation, Test, and Emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:464-471 [Journal]
  13. Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull
    Interactive presentation: Implementation of a transaction level assertion framework in SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:894-899 [Conf]
  14. Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull
    Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:767-772 [Conf]
  15. Wolfgang Ecker, Volkan Esen, Michael Hull
    Execution semantics and formalisms for multi-abstraction TLM assertions. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:93-102 [Conf]
  16. Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten
    Requirements and Concepts for Transaction Level Assertion Refinement. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:1-14 [Conf]

  17. Using a dataflow abstracted virtual prototype for HdS-design. [Citation Graph (, )][DBLP]


  18. Industrial IP Integration Flows based on IP-XACT Standards. [Citation Graph (, )][DBLP]


  19. Panel Session - Who Is Closing the embedded software design gap? [Citation Graph (, )][DBLP]


  20. TLM+ modeling of embedded HW/SW systems. [Citation Graph (, )][DBLP]


  21. VHDL-based communication and synchronization synthesis. [Citation Graph (, )][DBLP]


  22. A classification of design steps and their verification. [Citation Graph (, )][DBLP]


  23. Semi-dynamic scheduling of synchronization-mechanisms. [Citation Graph (, )][DBLP]


  24. Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. [Citation Graph (, )][DBLP]


  25. Requirements and Concepts for Transaction Level Assertions. [Citation Graph (, )][DBLP]


  26. Case Study on Transaction Level Modeling. [Citation Graph (, )][DBLP]


  27. IP Library For Temporal SystemC Assertions. [Citation Graph (, )][DBLP]


  28. SystemVerilog: Interface Based Design. [Citation Graph (, )][DBLP]


  29. Extending the RASSP model for Verification. [Citation Graph (, )][DBLP]


  30. The Formal Simulation Semantics of SystemVerilog. [Citation Graph (, )][DBLP]


  31. An Open VHDL-AMS Simulation Framework. [Citation Graph (, )][DBLP]


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