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Utz G. Baitinger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michael Ryba, Wolfram Seibold, Utz G. Baitinger, Ulrich Thelen
    Parameterized VHDL Entities for the Simulation of Hybrid Circuits. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:551-567 [Conf]
  2. Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger
    Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:459-0 [Conf]
  3. Utz G. Baitinger
    Hardware Design - A Tools View. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (3), 1994, pp:326-332 [Conf]
  4. Peter E. H. Hofmann, Utz G. Baitinger
    CoDO - Eine Entwurfsumgebung für verteilte objektorientierte CAE-Werkzeuge. [Citation Graph (0, 0)][DBLP]
    Kommunikation in Verteilten Systemen, 1997, pp:211-223 [Conf]
  5. Philipp Lanchès, Utz G. Baitinger
    Eine Umgebung zur Evaluierug paralleler Logiksimulationsverfahren. [Citation Graph (0, 0)][DBLP]
    Transputer-Anwender-Treffen, 1992, pp:61-71 [Conf]
  6. Philipp Lanchès, Utz G. Baitinger
    Parallele Vorverarbeitungsschritte für die verteilte Logiksimulation. [Citation Graph (0, 0)][DBLP]
    Transputer-Anwender-Treffen, 1992, pp:214-224 [Conf]
  7. Rainer Amann, Utz G. Baitinger
    Optimal state chains and state codes in finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:153-170 [Journal]
  8. Hans-Jorg Mathony, Utz G. Baitinger
    CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:3, pp:346-355 [Journal]

  9. A gate-matrix oriented partitioning approach for multilevel logical networks. [Citation Graph (, )][DBLP]

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