|
Search the dblp DataBase
Gerald E. Sobelman:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Lijun Gao, Sarvesh Shrivastava, Gerald E. Sobelman
Elliptic Curve Scalar Multiplier Design Using FPGAs. [Citation Graph (0, 0)][DBLP] CHES, 1999, pp:257-268 [Conf]
- David E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin
Automated layout synthesis in the YASC silicon compiler. [Citation Graph (0, 0)][DBLP] DAC, 1986, pp:447-453 [Conf]
- E. Vandris, Gerald E. Sobelman
Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation. [Citation Graph (0, 0)][DBLP] DAC, 1991, pp:138-143 [Conf]
- David E. Krekelberg, Gerald E. Sobelman, Chu S. Jhon
Yet another silicon compiler. [Citation Graph (0, 0)][DBLP] DAC, 1985, pp:176-182 [Conf]
- Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. [Citation Graph (0, 0)][DBLP] FCCM, 1999, pp:304-305 [Conf]
- Daewook Kim, Manho Kim, Gerald E. Sobelman
FPGA-Based CDMA Switch for Networks-on-Chip. [Citation Graph (0, 0)][DBLP] FCCM, 2005, pp:283-284 [Conf]
- Hanho Lee, Gerald E. Sobelman
Digit-Serial DSP Library for Optimized FPGA Configuration. [Citation Graph (0, 0)][DBLP] FCCM, 1998, pp:322-323 [Conf]
- Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman
FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). [Citation Graph (0, 0)][DBLP] FPGA, 1998, pp:257- [Conf]
- Hanho Lee, Gerald E. Sobelman
A New Low-Voltage Full Adder Circuit. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1997, pp:88-0 [Conf]
- E. Vandris, Gerald E. Sobelman
Fast Switch-Level Fault Simulation Using Functional Fault Modeling. [Citation Graph (0, 0)][DBLP] ICCAD, 1990, pp:74-77 [Conf]
- Kai-Chuan Chang, Gerald E. Sobelman, Ebrahim Saberinia, Ahmed H. Tewfik
Analysis of higher-order N-tone sigma-delta modulators for ultra wideband communications. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:113-116 [Conf]
- Ming-Ta Hsieh, Gerald E. Sobelman
Simultaneous bidirectional signaling with adaptive pre-emphasis. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:397-400 [Conf]
- Ming-Ta Hsieh, Gerald E. Sobelman
Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2005, pp:4883-4886 [Conf]
- Daewook Kim, Manho Kim, Gerald E. Sobelman
Parallel FFT computation with a CDMA-based network-on-chip. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2005, pp:1138-1141 [Conf]
- Gerald E. Sobelman, Donovan L. Raatz
Low-Power Multiplier Design Using Delayed Evaluation. [Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:1564-1567 [Conf]
- Kavitha Seshadri, Adrianne Pontarelli, Gauri Joglekar, Gerald E. Sobelman
Design techniques for Pulsed Static CMOS. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:929-932 [Conf]
- Gunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi
High-speed add-compare-select units using locally self-resetting CMOS. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:889-892 [Conf]
- Gunok Jung, V. A. Sundarajan, Gerald E. Sobelman
A robust self-resetting CMOS 32-bit parallel adder. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:473-476 [Conf]
- Sungwook Kim, Gerald E. Sobelman
Efficient digit-serial FIR filters with skew-tolerant domino. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2002, pp:369-372 [Conf]
- E. Vandris, Gerald E. Sobelman
A Mixed Functional/IDDQ Testing Methodology for CMOS Transistor Faults. [Citation Graph (0, 0)][DBLP] ITC, 1991, pp:608-614 [Conf]
- Qingquan Zhang, Gerald E. Sobelman, Tian He
Gradient-Driven Target Acquisition in Mobile Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP] MSN, 2006, pp:365-376 [Conf]
- Qingquan Zhang, Woong Cho, Gerald E. Sobelman, Liuqing Yang, Richard M. Voyles
TwinsNet: A Cooperative MIMO Mobile Sensor Network. [Citation Graph (0, 0)][DBLP] UIC, 2006, pp:508-516 [Conf]
- Rob Smith, Gerald E. Sobelman
Simulation-based design of programmable systolic arrays. [Citation Graph (0, 0)][DBLP] Computer-Aided Design, 1991, v:23, n:10, pp:669-675 [Journal]
- Hanho Lee, Gerald E. Sobelman
VLSI Design Of Digit-Serial FPGA Architecture. [Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2004, v:13, n:1, pp:17-52 [Journal]
- O. Melstrand, Eamonn O'Neill, Gerald E. Sobelman, D. Dokos
A Data Base Driven Automated System for MOS Device Characterization, Parameter Optimization and Modeling. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:1, pp:47-51 [Journal]
- Wen-Chih Kan, Gerald E. Sobelman
MIMO Transceiver Design Based on a Modified Geometric Mean Decomposition. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:677-680 [Conf]
- Daewook Kim, Manho Kim, Gerald E. Sobelman
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Manho Kim, Daewook Kim, Gerald E. Sobelman
Network-on-chip quality-of-service through multiprotocol label switching. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Ming-Ta Hsieh, Gerald E. Sobelman
Modeling and verification of high-speed wired links with Verilog-AMS. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Manho Kim, Daewook Kim, Gerald E. Sobelman
Network-on-chip link analysis under power and performance constraints. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Daewook Kim, Manho Kim, Gerald E. Sobelman
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Kai-Chuan Chang, Gerald E. Sobelman
Noise Model Analysis of Optimized Mixed-Radix Structures for Pulsed OFDM. [Citation Graph (0, 0)][DBLP] GLOBECOM, 2006, pp:- [Conf]
- Ebrahim Saberinia, K. C. Chang, Gerald E. Sobelman, Ahmed H. Tewfik
Implementation of a Multi-band Pulsed-OFDM Transceiver. [Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2006, v:43, n:1, pp:73-88 [Journal]
Adaptive quantization in min-sum based irregular LDPC decoder. [Citation Graph (, )][DBLP]
Low-Power Bus Transform Coding for Multilevel Signals. [Citation Graph (, )][DBLP]
FPGA-Based Design of a Pulsed-OFDM System. [Citation Graph (, )][DBLP]
Cscan: A Correlation-based Scheduling Algorithm for Wireless Sensor Networks. [Citation Graph (, )][DBLP]
High Speed Look-Ahead LMS Detector for MIMO Systems. [Citation Graph (, )][DBLP]
A heterogeneous reconfigurable baseband architecture for wireless LAN transceivers. [Citation Graph (, )][DBLP]
Search in 0.002secs, Finished in 0.327secs
|