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Gerald E. Sobelman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lijun Gao, Sarvesh Shrivastava, Gerald E. Sobelman
    Elliptic Curve Scalar Multiplier Design Using FPGAs. [Citation Graph (0, 0)][DBLP]
    CHES, 1999, pp:257-268 [Conf]
  2. David E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin
    Automated layout synthesis in the YASC silicon compiler. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:447-453 [Conf]
  3. E. Vandris, Gerald E. Sobelman
    Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:138-143 [Conf]
  4. David E. Krekelberg, Gerald E. Sobelman, Chu S. Jhon
    Yet another silicon compiler. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:176-182 [Conf]
  5. Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman
    A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:304-305 [Conf]
  6. Daewook Kim, Manho Kim, Gerald E. Sobelman
    FPGA-Based CDMA Switch for Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:283-284 [Conf]
  7. Hanho Lee, Gerald E. Sobelman
    Digit-Serial DSP Library for Optimized FPGA Configuration. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:322-323 [Conf]
  8. Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman
    FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:257- [Conf]
  9. Hanho Lee, Gerald E. Sobelman
    A New Low-Voltage Full Adder Circuit. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:88-0 [Conf]
  10. E. Vandris, Gerald E. Sobelman
    Fast Switch-Level Fault Simulation Using Functional Fault Modeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:74-77 [Conf]
  11. Kai-Chuan Chang, Gerald E. Sobelman, Ebrahim Saberinia, Ahmed H. Tewfik
    Analysis of higher-order N-tone sigma-delta modulators for ultra wideband communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:113-116 [Conf]
  12. Ming-Ta Hsieh, Gerald E. Sobelman
    Simultaneous bidirectional signaling with adaptive pre-emphasis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:397-400 [Conf]
  13. Ming-Ta Hsieh, Gerald E. Sobelman
    Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4883-4886 [Conf]
  14. Daewook Kim, Manho Kim, Gerald E. Sobelman
    Parallel FFT computation with a CDMA-based network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1138-1141 [Conf]
  15. Gerald E. Sobelman, Donovan L. Raatz
    Low-Power Multiplier Design Using Delayed Evaluation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1564-1567 [Conf]
  16. Kavitha Seshadri, Adrianne Pontarelli, Gauri Joglekar, Gerald E. Sobelman
    Design techniques for Pulsed Static CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:929-932 [Conf]
  17. Gunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi
    High-speed add-compare-select units using locally self-resetting CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:889-892 [Conf]
  18. Gunok Jung, V. A. Sundarajan, Gerald E. Sobelman
    A robust self-resetting CMOS 32-bit parallel adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:473-476 [Conf]
  19. Sungwook Kim, Gerald E. Sobelman
    Efficient digit-serial FIR filters with skew-tolerant domino. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:369-372 [Conf]
  20. E. Vandris, Gerald E. Sobelman
    A Mixed Functional/IDDQ Testing Methodology for CMOS Transistor Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:608-614 [Conf]
  21. Qingquan Zhang, Gerald E. Sobelman, Tian He
    Gradient-Driven Target Acquisition in Mobile Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    MSN, 2006, pp:365-376 [Conf]
  22. Qingquan Zhang, Woong Cho, Gerald E. Sobelman, Liuqing Yang, Richard M. Voyles
    TwinsNet: A Cooperative MIMO Mobile Sensor Network. [Citation Graph (0, 0)][DBLP]
    UIC, 2006, pp:508-516 [Conf]
  23. Rob Smith, Gerald E. Sobelman
    Simulation-based design of programmable systolic arrays. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1991, v:23, n:10, pp:669-675 [Journal]
  24. Hanho Lee, Gerald E. Sobelman
    VLSI Design Of Digit-Serial FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:1, pp:17-52 [Journal]
  25. O. Melstrand, Eamonn O'Neill, Gerald E. Sobelman, D. Dokos
    A Data Base Driven Automated System for MOS Device Characterization, Parameter Optimization and Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:1, pp:47-51 [Journal]
  26. Wen-Chih Kan, Gerald E. Sobelman
    MIMO Transceiver Design Based on a Modified Geometric Mean Decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:677-680 [Conf]
  27. Daewook Kim, Manho Kim, Gerald E. Sobelman
    DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Manho Kim, Daewook Kim, Gerald E. Sobelman
    Network-on-chip quality-of-service through multiprotocol label switching. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  29. Ming-Ta Hsieh, Gerald E. Sobelman
    Modeling and verification of high-speed wired links with Verilog-AMS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  30. Manho Kim, Daewook Kim, Gerald E. Sobelman
    Network-on-chip link analysis under power and performance constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  31. Daewook Kim, Manho Kim, Gerald E. Sobelman
    NIUGAP: low latency network interface architecture with Gray code for networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  32. Kai-Chuan Chang, Gerald E. Sobelman
    Noise Model Analysis of Optimized Mixed-Radix Structures for Pulsed OFDM. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  33. Ebrahim Saberinia, K. C. Chang, Gerald E. Sobelman, Ahmed H. Tewfik
    Implementation of a Multi-band Pulsed-OFDM Transceiver. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:1, pp:73-88 [Journal]

  34. Adaptive quantization in min-sum based irregular LDPC decoder. [Citation Graph (, )][DBLP]


  35. Low-Power Bus Transform Coding for Multilevel Signals. [Citation Graph (, )][DBLP]


  36. FPGA-Based Design of a Pulsed-OFDM System. [Citation Graph (, )][DBLP]


  37. Cscan: A Correlation-based Scheduling Algorithm for Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  38. High Speed Look-Ahead LMS Detector for MIMO Systems. [Citation Graph (, )][DBLP]


  39. A heterogeneous reconfigurable baseband architecture for wireless LAN transceivers. [Citation Graph (, )][DBLP]


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