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Catherine H. Gebotys: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Catherine H. Gebotys, Robert J. Gebotys
    Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:114-128 [Conf]
  2. Catherine H. Gebotys, Simon Ho, C. C. Tiu
    EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:250-264 [Conf]
  3. Catherine H. Gebotys
    Low energy security optimization in embedded cryptographic systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:224-229 [Conf]
  4. Catherine H. Gebotys, Y. Zhang
    Security wrappers and power analysis for SoC technologies. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:162-167 [Conf]
  5. Peter Marwedel, Catherine H. Gebotys
    Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:72- [Conf]
  6. Radu Muresan, Catherine H. Gebotys
    Current flattening in software and hardware for security applications. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:218-223 [Conf]
  7. Catherine H. Gebotys, B. A. White
    Methodology for attack on a Java-based PDA. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:94-99 [Conf]
  8. Catherine H. Gebotys
    Utilizing Memory Bandwidth in DSP Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:347-352 [Conf]
  9. Catherine H. Gebotys
    Optimal Scheduling and Allocation of Embedded VLSI Chips. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:116-119 [Conf]
  10. Catherine H. Gebotys
    Low Energy Memory and Register Allocation Using Network Flow. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:435-440 [Conf]
  11. Catherine H. Gebotys, Mohamed I. Elmasry
    VLSI Design Synthesis with Testability. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:16-21 [Conf]
  12. Catherine H. Gebotys, Mohamed I. Elmasry
    Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:2-7 [Conf]
  13. Catherine H. Gebotys, Robert J. Gebotys, S. Wiratunga
    Power minimization derived from architectural-usage of VLIW processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:308-311 [Conf]
  14. Catherine H. Gebotys, Robert J. Gebotys
    Application-Specific Architectures for Field-Programmable VLSI Technologies. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:124-131 [Conf]
  15. Catherine H. Gebotys, Robert J. Gebotys
    Optimized mapping of video applications to hardware-software for VLSI architectures. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:41-48 [Conf]
  16. Catherine H. Gebotys, Robert J. Gebotys
    Power Minimization in Heterogeneous Processing. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1996, pp:330-337 [Conf]
  17. Catherine H. Gebotys, Robert J. Gebotys
    Performance-Power Optimization of Memory Components for Complex Embedded Systems. [Citation Graph (0, 0)][DBLP]
    HICSS (5), 1997, pp:152-159 [Conf]
  18. Catherine H. Gebotys, Robert J. Gebotys
    Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability. [Citation Graph (0, 0)][DBLP]
    HICSS (3), 1998, pp:150-156 [Conf]
  19. Catherine H. Gebotys, Robert J. Gebotys
    Designing for Low Power in Complex Embedded DSP Systems. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  20. Catherine H. Gebotys
    Optimal synthesis of multichip architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:238-241 [Conf]
  21. Catherine H. Gebotys
    DSP address optimization using a minimum cost circulation technique. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:100-103 [Conf]
  22. Catherine H. Gebotys, Mohamed I. Elmasry
    A Global Optimization Approach for Architectural Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:258-261 [Conf]
  23. Catherine H. Gebotys, Radu Muresan
    Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:205-216 [Conf]
  24. Catherine H. Gebotys, Robert J. Gebotys
    An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:121-123 [Conf]
  25. Catherine H. Gebotys
    Security-Driven Exploration of Cryptography in DSP Cores. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:80-85 [Conf]
  26. Catherine H. Gebotys
    An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:41-0 [Conf]
  27. Radu Muresan, Catherine H. Gebotys
    Current consumption dynamics at instruction and program level for a VLIW DSP processor. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:130-135 [Conf]
  28. Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
    Special Session: Security on SoC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:192-194 [Conf]
  29. Catherine H. Gebotys, Robert J. Gebotys
    A Framework for Security on NoC Technologies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:113-120 [Conf]
  30. Catherine H. Gebotys, C. C. Tiu, X. Chen
    A Countermeasure for EM Attack of a Wireless PDA. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:544-549 [Conf]
  31. Catherine H. Gebotys, B. A. White
    A Phase Substitution Technique for DEMA of Embedded Cryptographic Systems. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:868-869 [Conf]
  32. Amir Khatibzadeh, Catherine H. Gebotys
    Enhanced Current-Balanced Logic (ECBL): An Area Efficient Solution to Secure Smart Cards against Differential Power Attack. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:898-899 [Conf]
  33. Tim Woo, Catherine H. Gebotys, Sagar Naik
    An Energy-Efficient Image Representation for Secure Mobile Systems. [Citation Graph (0, 0)][DBLP]
    NETWORKING, 2005, pp:126-137 [Conf]
  34. Sarita V. Adve, Doug Burger, Rudolf Eigenmann, Alasdair Rawsthorne, Michael D. Smith, Catherine H. Gebotys, Mahmut T. Kandemir, David J. Lilja, Alok N. Choudhary, Jesse Zhixi Fang, Pen-Chung Yew
    Changing Interaction of Compiler and Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:51-58 [Journal]
  35. Catherine H. Gebotys
    A minimum-cost circulation approach to DSP address-code generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:726-741 [Journal]
  36. Catherine H. Gebotys, Mohamed I. Elmasry
    Global optimization approach for architectural synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1266-1278 [Journal]
  37. Catherine H. Gebotys
    Design of secure cryptography against the threat of power-attacks in DSP-embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:92-113 [Journal]
  38. Catherine H. Gebotys
    A split-mask countermeasure for low-energy secure embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:3, pp:577-612 [Journal]
  39. Radu Muresan, Catherine H. Gebotys
    Instantaneous current modeling in a complex VLIW processor core. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:415-451 [Journal]
  40. Catherine H. Gebotys
    A table masking countermeasure for low-energy secure embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:740-753 [Journal]
  41. Catherine H. Gebotys
    Throughput optimized architectural synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:254-261 [Journal]
  42. Catherine H. Gebotys
    An optimization approach to the synthesis of multichip architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:11-20 [Journal]
  43. Catherine H. Gebotys
    A network flow approach to memory bandwidth utilization in embedded DSP core processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:390-398 [Journal]

  44. Novel Precomputation Schemes for Elliptic Curve Cryptosystems. [Citation Graph (, )][DBLP]


  45. Efficient Techniques for High-Speed Elliptic Curve Cryptography. [Citation Graph (, )][DBLP]


  46. Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC). [Citation Graph (, )][DBLP]


  47. Fast Multibase Methods and Other Several Optimizations for Elliptic Curve Scalar Multiplication. [Citation Graph (, )][DBLP]


  48. Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation. [Citation Graph (, )][DBLP]


  49. Forward-Secure Content Distribution to Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  50. Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals. [Citation Graph (, )][DBLP]


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