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Robert J. Gebotys: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Catherine H. Gebotys, Robert J. Gebotys
    Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:114-128 [Conf]
  2. Catherine H. Gebotys, Robert J. Gebotys, S. Wiratunga
    Power minimization derived from architectural-usage of VLIW processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:308-311 [Conf]
  3. Catherine H. Gebotys, Robert J. Gebotys
    Application-Specific Architectures for Field-Programmable VLSI Technologies. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:124-131 [Conf]
  4. Catherine H. Gebotys, Robert J. Gebotys
    Optimized mapping of video applications to hardware-software for VLSI architectures. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:41-48 [Conf]
  5. Catherine H. Gebotys, Robert J. Gebotys
    Power Minimization in Heterogeneous Processing. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1996, pp:330-337 [Conf]
  6. Catherine H. Gebotys, Robert J. Gebotys
    Performance-Power Optimization of Memory Components for Complex Embedded Systems. [Citation Graph (0, 0)][DBLP]
    HICSS (5), 1997, pp:152-159 [Conf]
  7. Catherine H. Gebotys, Robert J. Gebotys
    Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability. [Citation Graph (0, 0)][DBLP]
    HICSS (3), 1998, pp:150-156 [Conf]
  8. Catherine H. Gebotys, Robert J. Gebotys
    Designing for Low Power in Complex Embedded DSP Systems. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  9. Catherine H. Gebotys, Robert J. Gebotys
    An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:121-123 [Conf]
  10. Catherine H. Gebotys, Robert J. Gebotys
    A Framework for Security on NoC Technologies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:113-120 [Conf]

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