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Philip Heng Wai Leong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong, M. P. Leong
    Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA. [Citation Graph (0, 0)][DBLP]
    CHES, 2001, pp:333-347 [Conf]
  2. Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley
    Hardware efficient architectures for Eigenvalue computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:953-958 [Conf]
  3. T. K. Lee, Philip Heng Wai Leong, K. H. Lee, K. T. Chan, S. K. Hui, H. K. Yeung, M. F. Lo, J. H. M. Lee
    An FPGA Implementation of GENET for Solving Graph Coloring Problems . [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:284-285 [Conf]
  4. M. P. Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong
    A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:122-131 [Conf]
  5. Philip Heng Wai Leong, P. K. Tsang, T. K. Lee
    A FPGA Based Forth Microprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:254-255 [Conf]
  6. M. P. Leong, M. Y. Yeung, C. K. Yeung, C. W. Fu, P. A. Heng, Philip Heng Wai Leong
    Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:240-248 [Conf]
  7. K. H. Leung, K. W. Ma, W. K. Wong, Philip Heng Wai Leong
    FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:68-76 [Conf]
  8. Stanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, Philip Heng Wai Leong
    FPGA-based SIMD Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:267-268 [Conf]
  9. Kuen Hung Tsoi, Chun Hok Ho, H. C. Yeung, Philip Heng Wai Leong
    An Arithmetic Library and Its Application to the N-body Problem. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:68-78 [Conf]
  10. Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
    A Massively Parallel RC4 Key Search Engine. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:13-21 [Conf]
  11. Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong
    Compact FPGA-based True and Pseudo Random Number Generators. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:51-61 [Conf]
  12. Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, S. Lopez-Buedo
    Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:35-44 [Conf]
  13. Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton
    A synthesizable datapath-oriented embedded FPGA fabric. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:33-41 [Conf]
  14. Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
    Fly - A Modifiable Hardware Compiler. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:381-390 [Conf]
  15. Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
    IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:526-535 [Conf]
  16. Kurt K. Ting, Steve C. L. Yuen, Kin-Hong Lee, Philip Heng Wai Leong
    An FPGA Based SHA-256 Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:577-585 [Conf]
  17. Kuen Hung Tsoi, Philip Heng Wai Leong
    Mullet - A Parallel Multiplier Generator. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:691-694 [Conf]
  18. C. W. Yu, K. H. Kwong, Kin-Hong Lee, Philip Heng Wai Leong
    A Smith-Waterman Systolic Cell. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:375-384 [Conf]
  19. Wong Hiu Yung, Wing Seung Yuen, Kin-Hong Lee, Philip Heng Wai Leong
    A Runtime Reconfigurable Implementation of the GSAT Algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:526-531 [Conf]
  20. Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk
    Ziggurat-based Hardware Gaussian Random Number Generator. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:275-280 [Conf]
  21. Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K. C. Tsang, Bertram Emil Shi
    Implementation of Gabor-Type Filters on Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:327-328 [Conf]
  22. C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
    Dynamic Voltage Scaling for Commercial FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:173-180 [Conf]
  23. G. L. Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, C. C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk
    Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:215-222 [Conf]
  24. C. K. Chung, Philip Heng Wai Leong
    An Architecture for Solving Boolean Satisfiability Using Runtime Configurable Hardware. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 1999, pp:352-0 [Conf]
  25. Johnny M. H. Lee, Steve C. L. Yuen, Wen J. Li, Philip Heng Wai Leong
    Development of an AA size energy transducer with micro resonators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:876-879 [Conf]
  26. Chun Hok Ho, M. P. Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner
    Rapid Prototyping of FPGA Based Floating Point DSP Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:19-24 [Conf]
  27. Monk-Ping Leong, Chi Chiu Cheung, Chin-Wang Cheung, Polly P. M. Wan, Ivan K. H. Leung, Winnie M. M. Yeung, Wing Seung Yuen, Kenneth S. K. Chow, Kwong-Sak Leung, Philip Heng Wai Leong
    CPE: A Parallel Library for Financial Engineering Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:10, pp:70-77 [Journal]
  28. Philip Heng Wai Leong, Marwan A. Jabri
    Kakadu - A Low Power Analogue Neural Network Classifier. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1993, v:4, n:4, pp:381-394 [Journal]
  29. Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong
    A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:6, pp:659-671 [Journal]
  30. Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong
    A hardware Gaussian noise generator using the Wallace method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:911-920 [Journal]
  31. C. K. Wong, Philip Heng Wai Leong
    An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  32. David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor
    Gaussian random number generators. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 2007, v:39, n:4, pp:- [Journal]
  33. Philip Heng Wai Leong, C. W. Sham, W. C. Wong, H. Y. Wong, Wing Seung Yuen, Monk-Ping Leong
    A bitstream reconfigurable FPGA implementation of the WSAT algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:197-201 [Journal]
  34. Philip Heng Wai Leong, Isvan K. H. Leung
    A microcoded elliptic curve processor using FPGA technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:550-559 [Journal]

  35. Recent Trends in FPGA Architectures and Applications. [Citation Graph (, )][DBLP]


  36. Map-reduce as a Programming Model for Custom Computing Machines. [Citation Graph (, )][DBLP]


  37. FPGA interconnect design using logical effort. [Citation Graph (, )][DBLP]


  38. A comparison of via-programmable gate array logic cell circuits. [Citation Graph (, )][DBLP]


  39. Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. [Citation Graph (, )][DBLP]


  40. FPGA interconnect design using logical effort. [Citation Graph (, )][DBLP]


  41. Mapping and scheduling with task clustering for heterogeneous computing systems. [Citation Graph (, )][DBLP]


  42. Rapid estimation of power consumption for hybrid FPGAs. [Citation Graph (, )][DBLP]


  43. An analytical model describing the relationships between logic architecture and FPGA density. [Citation Graph (, )][DBLP]


  44. Modeling post-techmapping and post-clustering FPGA circuit depth. [Citation Graph (, )][DBLP]


  45. A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering. [Citation Graph (, )][DBLP]


  46. Development of a Human Airbag System for Fall Protection Using MEMS Motion Sensing Technology. [Citation Graph (, )][DBLP]


  47. A Novel Real-Time Error Compensation Methodology for ?IMU-based Digital Writing Instrument. [Citation Graph (, )][DBLP]


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