The SCEAS System
Navigation Menu

Search the dblp DataBase


William P. Marnane: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto
    Efficient Hardware for the Tate Pairing Calculation in Characteristic Three. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:412-426 [Conf]
  2. Alan Daly, William P. Marnane
    Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:40-49 [Conf]
  3. Stephen J. Bellis, William P. Marnane
    A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:485-494 [Conf]
  4. Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici
    Fast Modular Division for Application in ECC on Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:786-795 [Conf]
  5. Maurice Keller, Tim Kerins, William P. Marnane
    FPGA Implementation of a GF(24M) Multiplier for use in Pairing Based Cryptosystems. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:594-597 [Conf]
  6. Tim Kerins, Emanuel M. Popovici, William P. Marnane
    Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:74-83 [Conf]
  7. Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick
    Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2). [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:750-759 [Conf]
  8. William P. Marnane, C. N. Jordan, F. J. O'Reilly
    Compiling Regular Arrays onto FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:178-187 [Conf]
  9. Henrik Eriksson, Per Larsson-Edefors, William P. Marnane
    A regular parallel multiplier which utilizes multiple carry-propagate adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:166-169 [Conf]
  10. Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy, William P. Marnane
    Optimisation of the SHA-2 Family of Hash Functions on FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:317-322 [Conf]
  11. Francis M. Crowe, Alan Daly, William P. Marnane
    A Scalable Dual Mode Arithmetic Unit for Public Key Cryptosystems. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:568-573 [Conf]
  12. Robert Ronan, Colm O'Eigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins, William P. Marnane
    An Embedded Processor for a Pairing-Based Cryptosystem. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:192-197 [Conf]
  13. A. Byrne, Nicolas Meloni, Francis M. Crowe, William P. Marnane, Arnaud Tisserand, Emanuel M. Popovici
    SPA resistant Elliptic Curve Cryptosystem using Addition Chains. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:995-1000 [Conf]
  14. Stephen Faul, Gregor Gregorcic, Geraldine Boylan, William P. Marnane, Gordon Lightbody, Sean Connolly
    Gaussian Process Modelling as an Indicator of Neonatal Seizure. [Citation Graph (0, 0)][DBLP]
    SPPRA, 2006, pp:177-182 [Conf]
  15. Myles H. Capstick, William P. Marnane, Ronald Pethig
    Biologic Computational Building Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:11, pp:22-29 [Journal]
  16. Tim Kerins, William P. Marnane, Emanuel M. Popovici
    Versatile hardware architectures for GF(pm) arithmetic in public key cryptography. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:1, pp:28-35 [Journal]
  17. Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici
    An FPGA implementation of a GF(p) ALU for encryption processors. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:253-260 [Journal]
  18. Maria Carmen Perez, Jesús Ureña, Álvaro Hernández, Carlos De Marziani, A. Ochoa, William P. Marnane
    FPGA Implementation of an Efficient Correlator for Complementary Sets of Sequences. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  19. Maurice Keller, William P. Marnane
    Low Power Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:310-319 [Conf]
  20. Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane
    FPGA Implementation of a GF(2m) Tate Pairing Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:358-369 [Conf]
  21. Maurice Keller, Robert Ronan, William P. Marnane, Colin C. Murphy
    Hardware architectures for the Tate pairing over GF(2m). [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:5-6, pp:392-406 [Journal]

  22. FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash. [Citation Graph (, )][DBLP]

  23. Energy Efficient Elliptic Curve Processor. [Citation Graph (, )][DBLP]

  24. Distinguishing Multiplications from Squaring Operations. [Citation Graph (, )][DBLP]

  25. Differential Power Analysis of HMAC Based on SHA-2, and Countermeasures. [Citation Graph (, )][DBLP]

  26. Unknown Plaintext Template Attacks. [Citation Graph (, )][DBLP]

  27. A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem. [Citation Graph (, )][DBLP]

  28. A Reconfigurable Implementation of the Tate Pairing Computation over GF(2m). [Citation Graph (, )][DBLP]

  29. FPGA Implementations of LDPC over GF(2m) Decoders. [Citation Graph (, )][DBLP]

  30. Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC. [Citation Graph (, )][DBLP]

  31. FPGA Implementation of an Elliptic Curve Processor Using the GLV Method. [Citation Graph (, )][DBLP]

Search in 0.004secs, Finished in 0.007secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002