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Publications of Author

1. Viktor Fischer, Milos Drutarovský
   Two Methods of Rijndael Implementation in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   CHES, 2001, pp:77-92 [Conf]
   
2. Viktor Fischer, Milos Drutarovský
   True Random Number Generator Embedded in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   CHES, 2002, pp:415-430 [Conf]
   
3. Martin Simka, Jan Pelzl, Thorsten Kleinjung, Jens Franke, Christine Priplata, Colin Stahlke, Milos Drutarovský, Viktor Fischer
   Hardware Factorization Based on Elliptic Curve Method. [Citation Graph (0, 0)][DBLP]
   FCCM, 2005, pp:107-116 [Conf]
   
4. Milos Drutarovský, Viktor Fischer
   Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1146-1148 [Conf]
   
5. Viktor Fischer, Milos Drutarovský, Rastislav Lukac
   Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:720-729 [Conf]
   
6. Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard
   High Performance True Random Number Generator in Altera Stratix FPLDs. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:555-564 [Conf]
   
7. Martin Simka, Viktor Fischer, Milos Drutarovský
   Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:1075-1078 [Conf]
   
8. Viktor Fischer, Lionel Torres, Daniel Mesquita
   Flexible security and its technology limits. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:243-248 [Conf]
   
9. Milos Drutarovský, Martin Simka, Viktor Fischer, Frederic Celle
   A Simple PLL-Based True Random Number Generator for Embedded Digital Systems. [Citation Graph (0, 0)][DBLP]
   Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
   
10. Viktor Fischer, Milos Drutarovský, Pawel Chodowiec, F. Gramain
    InvMixColumn decomposition and multilevel resource sharing in AES implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:989-992 [Journal]
    
11. Martin Simka, Milos Drutarovský, Viktor Fischer, J. Fayolle
    Model of a true random number generator aimed at cryptographic applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
12. 
    Modeling and observing the jitter in ring oscillators implemented in FPGAs. [Citation Graph (, )][DBLP]
    
    
13. 
    Enhancing security of ring oscillator-based trng implemented in FPGA. [Citation Graph (, )][DBLP]
    
    
14. 
    Efficient AES S-boxes implementation for non-volatile FPGAs. [Citation Graph (, )][DBLP]
    
    
15. 
    Observing the Randomness in RO-Based TRNG. [Citation Graph (, )][DBLP]
    
    
16. 
    Adaptive FPGA NoC-based Architecture for Multispectral Image Correlation [Citation Graph (, )][DBLP]