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Cameron Patterson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cameron Patterson
    A Dynamic FPGA Implementation of the Serpent Block Cipher. [Citation Graph (0, 0)][DBLP]
    CHES, 2000, pp:141-155 [Conf]
  2. Cameron Patterson
    A Dynamic Module Server for Embedded Platform FPGAs. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:31-40 [Conf]
  3. Jesse Hunter, Peter Athanas, Cameron Patterson
    VTSim: A Virtex-II Device Simulator. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:297-298 [Conf]
  4. James Hwang, Cameron Patterson, Sujoy Mitra
    VHDL Placement Directives for Parametric IP Blocks. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:284-285 [Conf]
  5. Cameron Patterson
    High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm). [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:113-121 [Conf]
  6. James Hwang, Cameron Patterson, Sujoy Mitra
    Hierarchical Placement Directives for Parametric IP Blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:250- [Conf]
  7. James Hwang, Cameron Patterson, S. Mohan, Eric Dellinger, Sujoy Mitra, Ralph Wittig
    Generating Layouts for Self-implementing Modules. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:525-529 [Conf]
  8. Scott McMillan, Cameron Patterson
    JBitsTM Implementations of the Advanced Encryption Standard (Rijndael). [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:162-171 [Conf]
  9. Alexandra Poetter, Jesse Hunter, Cameron Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner
    JHDLBits: The Merging of Two Worlds. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:414-423 [Conf]
  10. Tim Price, Cameron Patterson
    Reconfigurable Breakpoints for Co-debug. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:473-482 [Conf]
  11. Stephen D. Craven, Cameron Patterson, Peter M. Athanas
    A Methodology for Generating Application-Specific Heterogeneous Processor Arrays. [Citation Graph (0, 0)][DBLP]
    HICSS, 2006, pp:- [Conf]

  12. Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. [Citation Graph (, )][DBLP]

  13. Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing. [Citation Graph (, )][DBLP]

  14. Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip. [Citation Graph (, )][DBLP]

  15. An efficient run-time router for connecting modules in FPGAS. [Citation Graph (, )][DBLP]

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