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Amit Singh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Steven Trimberger, Raymond Pang, Amit Singh
    A 12 Gbps DES Encryptor/Decryptor Core in an FPGA. [Citation Graph (0, 0)][DBLP]
    CHES, 2000, pp:156-163 [Conf]
  2. Amit Singh, Hakan Ferhatosmanoglu, Ali Saman Tosun
    High dimensional reverse nearest neighbor queries. [Citation Graph (0, 0)][DBLP]
    CIKM, 2003, pp:91-98 [Conf]
  3. Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    Latency and Latch Count Minimization in Wave Steered Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:383-388 [Conf]
  4. Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    A Global Routing Technique for Wave-Steering Design Methodology. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:430-437 [Conf]
  5. Amit Singh, Malgorzata Marek-Sadowska
    Efficient circuit clustering for area and power reduction in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:59-66 [Conf]
  6. Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    Interconnect pipelining in a throughput-intensive FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:153-160 [Conf]
  7. Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
    A novel high throughput reconfigurable FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:22-29 [Conf]
  8. Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
    Interconnect Resource-Aware Placement for Hierarchical FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:132-136 [Conf]
  9. Amit Singh, Malgorzata Marek-Sadowska
    Circuit clustering using graph coloring. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:164-169 [Conf]
  10. Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh
    Interconnect complexity-aware FPGA placement using Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:115-121 [Conf]
  11. Amit Singh, Malgorzata Marek-Sadowska
    FPGA interconnect planning. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:23-30 [Conf]
  12. José Carlos Brustoloni, Eran Gabber, Abraham Silberschatz, Amit Singh
    Signaled Receiver Processing. [Citation Graph (0, 0)][DBLP]
    USENIX Annual Technical Conference, General Track, 2000, pp:211-224 [Conf]
  13. Sanket Shah, Tularam M. Bansod, Amit Singh
    Design and Implementation of a Network Processor Based 10Gbps Network Traffic Generator. [Citation Graph (0, 0)][DBLP]
    ICDCN, 2006, pp:269-275 [Conf]
  14. Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
    Efficient circuit clustering for area and power reduction in FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:643-663 [Journal]
  15. Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska
    PITIA: an FPGA for throughput-intensive applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:354-363 [Journal]

  16. Collective annotation of Wikipedia entities in web text. [Citation Graph (, )][DBLP]


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