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Alessandro Trifiletti: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti
    Three-Phase Dual-Rail Pre-charge Logic. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:232-241 [Conf]
  2. Jacopo Giorgetti, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti
    Analysis of data dependence of leakage current in CMOS cryptographic hardware. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:78-83 [Conf]
  3. Mauro Olivieri, Alessandro Trifiletti, Alessandro De Gloria
    A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:476-481 [Conf]
  4. Manfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
    A novel CMOS logic style with data independent power consumption. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1066-1069 [Conf]
  5. Marco Balsi, Francesco Centurelli, Giuseppe Scotti, P. Tommasino, Alessandro Trifiletti
    An accurate behavioral model of phase detectors for clock recovery circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:636-639 [Conf]
  6. Francesco Centurelli, Stefano Costi, Mauro Olivieri, Salvatore Pennisi, Alessandro Trifiletti
    Robust three-state PFD architecture with enhanced frequency acquisition capabilities. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:812-815 [Conf]
  7. Francesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
    High-speed CMOS-to-ECL pad driver in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:448-451 [Conf]
  8. Francesco Centurelli, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
    A high-speed low-voltage phase detector for clock recovery from NRZ data. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:297-300 [Conf]
  9. Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
    CMOS single-to-differential current amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2583-2586 [Conf]
  10. Mauro Olivieri, Alessandro Trifiletti
    An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:638-641 [Conf]
  11. Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti
    A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:67-72 [Conf]
  12. Marco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti
    A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:481-490 [Conf]
  13. Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti
    Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:119-128 [Conf]
  14. Andrea Pallotta, Francesco Centurelli, Francesco Loriga, Alessandro Trifiletti
    A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology. [Citation Graph (0, 0)][DBLP]
    SYBEN, 1998, pp:183-190 [Conf]
  15. Marco Bucci, Lucia Germani, Raimondo Luzzi, Alessandro Trifiletti, Mario Varanonuovo
    A High-Speed Oscillator-Based Truly Random Number Source for Cryptographic Applications on a Smart Card IC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:403-409 [Journal]
  16. Francesco Centurelli, A. Golfarelli, J. Guinea, L. Masini, D. Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
    A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:191-200 [Journal]
  17. Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
    A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:630-638 [Journal]
  18. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
    A distortion model for pipeline Analog-to-Digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3387-3390 [Conf]
  19. Christian Falconi, M. Cianella, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
    Mismatch-tolerant, Continuous Time, Gain Enhanced Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2204-2207 [Conf]
  20. Christian Falconi, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
    Low Voltage CMOS Current and Voltage References without Resistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1907-1910 [Conf]
  21. Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Salvatore Pennisi
    Source-degenerated CMOS Transconductor with Auxiliary Linearization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2240-2243 [Conf]
  22. Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
    150 µA CMOS Transconductor with 82 dB SFDR. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:237-240 [Conf]
  23. Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
    Inverting closed-loop amplifier architecture with reduced gain error and high input impedance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  24. Marco Bucci, Luca Giancane, Raimondo Luzzi, Mario Varanonuovo, Alessandro Trifiletti
    A novel concept for stateless random bit generators in cryptographic applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  25. Manfred Josef Aigner, Stefan Mangard, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Thomas Popp, Giuseppe Scotti, Alessandro Trifiletti
    Side channel analysis resistant design flow. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  26. Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti
    Enhancing power analysis attacks against cryptographic devices. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Marco Balsi, Francesco Centurelli, Piero Marietti, Giuseppe Scotti, P. Tommasino, Alessandro Trifiletti, G. Valente
    Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
    A model for the distortion due to switch on-resistance in sample-and-hold circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  29. Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
    A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:516-525 [Conf]
  30. Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti
    A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Dependable Sec. Comput., 2007, v:4, n:4, pp:245-251 [Journal]
  31. Mauro Olivieri, Simone Smorfa, Alessandro Trifiletti
    Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:309-318 [Journal]

  32. 10-th order programmable low-pass CMOS integrated pulse-shaping filter. [Citation Graph (, )][DBLP]


  33. A countermeasure against differential power analysis based on random delay insertion. [Citation Graph (, )][DBLP]


  34. Optimized design of source coupled logic gates in GaAs HEMT technology. [Citation Graph (, )][DBLP]


  35. Mixed-signal flexible architecture for the synthesis of n-port networks. [Citation Graph (, )][DBLP]


  36. Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems. [Citation Graph (, )][DBLP]


  37. Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems. [Citation Graph (, )][DBLP]


  38. A gain-enhancing technique for very low-voltage amplifiers. [Citation Graph (, )][DBLP]


  39. Differential Capacitance Analysis. [Citation Graph (, )][DBLP]


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