The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Georgi Kuzmanov: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
    Improving SHA-2 Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:298-310 [Conf]
  2. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    Visual Data Rectangular Memory. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:760-767 [Conf]
  3. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    The MOLEN Processor Prototype. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:296-299 [Conf]
  4. Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G. N. Gaydadjiev
    64-bit floating-point FPGA matrix multiplication. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:86-95 [Conf]
  5. Georgi Kuzmanov, Stamatis Vassiliadis
    Arbitrating Instructions in an pmu-Coded CCM. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:81-90 [Conf]
  6. Georgi Kuzmanov, Stamatis Vassiliadis
    Reconfigurable repetitive padding unit. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:98-103 [Conf]
  7. Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, Leonel Sousa
    Reconfigurable memory based AES co-processor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  8. Sascha Uhrig, S. Maier, Georgi Kuzmanov, Theo Ungerer
    Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  9. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    Loading rho-µ-Code: Design Considerations. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:11-19 [Conf]
  10. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    The Virtex II ProTM MOLEN Processor. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:192-202 [Conf]
  11. Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven
    A 2D Addressing Mode for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:291-306 [Conf]
  12. Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
    Rescheduling for Optimized SHA-1 Calculation. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:425-434 [Conf]
  13. Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte
    The MOLEN Polymorphic Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1363-1375 [Journal]
  14. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    Multimedia rectangularly addressable memory. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2006, v:8, n:2, pp:315-322 [Journal]
  15. Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven
    Hardwired MPEG-4 repetitive padding. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2005, v:7, n:2, pp:261-268 [Journal]
  16. Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz
    PISC: Polymorphic Instruction Set Computers. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:274-286 [Conf]

  17. Wave field synthesis for 3D audio: architectural prospectives. [Citation Graph (, )][DBLP]


  18. Memory Organization with Multi-Pattern Parallel Accesses. [Citation Graph (, )][DBLP]


  19. Merged Computation for Whirlpool Hashing. [Citation Graph (, )][DBLP]


  20. A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC. [Citation Graph (, )][DBLP]


  21. A 3d-audio reconfigurable processor. [Citation Graph (, )][DBLP]


  22. HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. [Citation Graph (, )][DBLP]


  23. DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator. [Citation Graph (, )][DBLP]


  24. On-the-fly attestation of reconfigurable hardware. [Citation Graph (, )][DBLP]


  25. BRAM-LUT Tradeoff on a Polymorphic DES Design. [Citation Graph (, )][DBLP]


  26. SAMS multi-layout memory: providing multiple views of data to boost SIMD performance. [Citation Graph (, )][DBLP]


  27. Reconfigurable accelerator for WFS-based 3D-audio. [Citation Graph (, )][DBLP]


  28. Reconfigurable Multithreading Architectures: A Survey. [Citation Graph (, )][DBLP]


  29. A reconfigurable beamformer for audio applications. [Citation Graph (, )][DBLP]


Search in 0.004secs, Finished in 0.005secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002