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Naofumi Homma: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh
    High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:187-200 [Conf]
  2. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Multiplier Block Synthesis Using Evolutionary Graph Generation. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:79-82 [Conf]
  3. Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi
    A framework of evolutionary graph generation system and its application to circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:201-204 [Conf]
  4. Naofumi Homma, Jun Sakiyama, Taihei Wakamatsu, Takafumi Aoki, Tatsuo Higuchi
    A systematic approach for analyzing fast addition algorithms using counter tree diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:197-200 [Conf]
  5. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Evolutionary graph generation system with transmigration capability for arithmetic circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:171-174 [Conf]
  6. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:2- [Conf]
  7. Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:334-339 [Conf]
  8. Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    PPSN, 2002, pp:831-840 [Conf]
  9. Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. [Citation Graph (0, 0)][DBLP]
    PPSN, 2004, pp:342-351 [Conf]
  10. Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi
    Evolutionary Synthesis of Arithmetic Circuit Structures. [Citation Graph (0, 0)][DBLP]
    Artif. Intell. Rev., 2003, v:20, n:3-4, pp:199-232 [Journal]
  11. Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshiki Terasaki, Tatsuo Higuchi
    Graph-based evolutionary design of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2002, v:6, n:1, pp:86-100 [Journal]
  12. Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
    SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1847-1850 [Conf]
  13. Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh
    DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1807-1810 [Conf]
  14. Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
    A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1859-1862 [Conf]

  15. High-Performance Concurrent Error Detection Scheme for AES Hardware. [Citation Graph (, )][DBLP]


  16. Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. [Citation Graph (, )][DBLP]


  17. Chosen-message SPA attacks against FPGA-based RSA hardware implementations. [Citation Graph (, )][DBLP]


  18. Application of symbolic computer algebra to arithmetic circuit verification. [Citation Graph (, )][DBLP]


  19. Systematic design of high-radix Montgomery multipliers for RSA processors. [Citation Graph (, )][DBLP]


  20. Enhanced power analysis attack using chosen message against RSA hardware implementations. [Citation Graph (, )][DBLP]


  21. Arithmetic module generator with algorithm optimization capability. [Citation Graph (, )][DBLP]


  22. High-performance ASIC implementations of the 128-bit block cipher CLEFIA. [Citation Graph (, )][DBLP]


  23. High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. [Citation Graph (, )][DBLP]


  24. Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. [Citation Graph (, )][DBLP]


  25. Multiple-Valued Constant-Power Adder for Cryptographic Processors. [Citation Graph (, )][DBLP]


  26. Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors. [Citation Graph (, )][DBLP]


  27. Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. [Citation Graph (, )][DBLP]


  28. Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. [Citation Graph (, )][DBLP]


  29. VLSI circuit design using an object-oriented framework of evolutionary graph generation system. [Citation Graph (, )][DBLP]


  30. Enhanced Correlation Power Analysis Using Key Screening Technique. [Citation Graph (, )][DBLP]


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