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Jean-Luc Dekeyser: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ahmad Chadi Aljundi, Jean-Luc Dekeyser, Isaac D. Scherson
    An Interconnection Networks Comparative Performance Evaluation Methodology: Delta and Over-Sized Delta Networks. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2003, pp:1-8 [Conf]
  2. Jean-Luc Dekeyser, Philippe Marquet
    Supporting Irregular and Dynamic Computations in Data Parallel Languages. [Citation Graph (0, 0)][DBLP]
    The Data Parallel Programming Model, 1996, pp:197-219 [Conf]
  3. Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser
    Estimating Energy Consumption for an MPSoC Architectural Exploration. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:298-310 [Conf]
  4. Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser
    Massively parallel processing on a chip. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:277-286 [Conf]
  5. Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser
    FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:280-287 [Conf]
  6. Dominique Sueur, Jean-Luc Dekeyser
    Dynamic Redistribution on Heterogeneous Parallel Computers. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:173-177 [Conf]
  7. Cyril Fonlupt, Jean-Luc Dekeyser, Philippe Marquet
    Dynamic Load Balancing on SIMD Data-Parallel Computers. [Citation Graph (0, 0)][DBLP]
    EUROSIM, 1994, pp:219-226 [Conf]
  8. Akram-Djellal Benalia, Jean-Luc Dekeyser, Philippe Marquet
    HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages. [Citation Graph (0, 0)][DBLP]
    HCI (2), 1993, pp:591-596 [Conf]
  9. Fabien Banse, Jean-Luc Dekeyser, Renaud Fauquembergue, François Dessenne
    Implementation of a Bi-Parallel Monte Carlo Device Simulation on Two Architectures. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1998, pp:193-202 [Conf]
  10. Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser
    A Data-Parallel View of the Load Balancing - Experimental Results on MasPar MP-1. [Citation Graph (0, 0)][DBLP]
    HPCN, 1994, pp:338-343 [Conf]
  11. Dominique Sueur, Jean-Luc Dekeyser, Philippe Marquet
    DPFS: A Data-Parallel File System Environment. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1998, pp:940-942 [Conf]
  12. Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet
    Mode-Automata Based Methodology for Scade. [Citation Graph (0, 0)][DBLP]
    HSCC, 2005, pp:386-401 [Conf]
  13. Samy Meftali, Jean-Luc Dekeyser
    SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool. [Citation Graph (0, 0)][DBLP]
    Virtual Enterprises and Collaborative Networks, 2004, pp:387-394 [Conf]
  14. Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson
    A Study of an Evaluation Methodology for Unbuffered Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:277- [Conf]
  15. Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser
    Real-time systems for multiprocessor architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  16. Samy Meftali, Jean-Luc Dekeyser
    An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:55-58 [Conf]
  17. Julien Soula, Philippe Marquet, Alain Demeure, Jean-Luc Dekeyser
    Compilation Principle of a Specification Language Dedicated to Signal Processing. [Citation Graph (0, 0)][DBLP]
    PaCT, 2001, pp:358-370 [Conf]
  18. A. Amar, Pierre Boulet, Jean-Luc Dekeyser, T. Theeuwen
    Distributed Process Networks - Using Half FIFO Queues in CORBA. [Citation Graph (0, 0)][DBLP]
    PARCO, 2003, pp:31-38 [Conf]
  19. Emmanuel Cagniot, Jean-Luc Dekeyser, Pierre Boulet, Thomas Brandes, Francis Piriou, Georges Marques
    Parallelization of a 3D Magnetostatic Code Using High Performance Fortran. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2000, pp:181-185 [Conf]
  20. Florent Devin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet
    GASPARD - A Visual Parallel Programming Environment. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2002, pp:145-150 [Conf]
  21. Ahmad Chadi Aljundi, Jean-Luc Dekeyser
    The Effect of the Degree of Multistage Interconnection Networks on their Performance: The Case of Delta and Over-Sized Delta Networks. [Citation Graph (0, 0)][DBLP]
    PDP, 2004, pp:72-0 [Conf]
  22. Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser
    Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. [Citation Graph (0, 0)][DBLP]
    PPAM, 2005, pp:896-903 [Conf]
  23. Jean-Luc Dekeyser, Christian Lefebvre
    Step By Step Transformation of a Fortran 90 Program in HPF, using HPF-Builder. [Citation Graph (0, 0)][DBLP]
    PPSC, 1997, pp:- [Conf]
  24. Jean-Luc Dekeyser, Dominique Sueur
    Data Parallel File System. [Citation Graph (0, 0)][DBLP]
    PPSC, 1997, pp:- [Conf]
  25. Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena
    Model Driven Engineering for Regular MPSoC Co-design. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:129-136 [Conf]
  26. Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet
    Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. [Citation Graph (0, 0)][DBLP]
    MoDELS, 2005, pp:445-459 [Conf]
  27. Jean-Luc Dekeyser, Boris Kokoszko, Jean-Luc Levaire, Philippe Marquet
    Irregular Data-Parallel Objects in C++. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1996, pp:65-80 [Conf]
  28. Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, Francis Piriou, Pierre Boulet, Stéphance Clénet
    High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2000, pp:519-528 [Conf]
  29. Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson
    A universal performance factor for multi-criteria evaluation of multistage interconnection networks. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2006, v:22, n:7, pp:794-804 [Journal]
  30. Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser
    Data-Parallel Load Balancing Strategies. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1998, v:24, n:11, pp:1665-1684 [Journal]
  31. M. Tahar Kechadi, Jean-Luc Dekeyser
    Analysis and Simulation of an Out-Of-Order Execution Model in Vector Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1997, v:23, n:13, pp:1963-1986 [Journal]
  32. Jean-Luc Dekeyser, Dominique Lazure, Philippe Marquet
    A Geometrical Data-Parallel Language. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 1994, v:29, n:4, pp:31-40 [Journal]
  33. Jean-Luc Dekeyser, Philippe Marquet, Ph. Pruex
    EVA: an explicit vector language. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 1990, v:25, n:8, pp:53-71 [Journal]
  34. Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser
    Multiple Abstraction Views of FPGA to Map Parallel Applications. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:90-97 [Conf]
  35. Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser
    An MPSoC Performance Estimation Framework Using Transaction Level Modeling. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:525-533 [Conf]

  36. An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. [Citation Graph (, )][DBLP]


  37. A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. [Citation Graph (, )][DBLP]


  38. Model-Driven Design of Embedded Multimedia Applications on SoCs. [Citation Graph (, )][DBLP]


  39. MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. [Citation Graph (, )][DBLP]


  40. A Design Flow to Map Parallel Applications onto FPGAs. [Citation Graph (, )][DBLP]


  41. Traceability Mechanism for Error Localization in Model Transformation. [Citation Graph (, )][DBLP]


  42. Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT. [Citation Graph (, )][DBLP]


  43. Using an MDE Approach for Modeling of Interconnection Networks. [Citation Graph (, )][DBLP]


  44. Scalable Multistage Network for Multiprocessor System-on-Chip Design. [Citation Graph (, )][DBLP]


  45. Modeling and Formal Validation of High-Performance Embedded Systems. [Citation Graph (, )][DBLP]


  46. A Graphical Framework for High Performance Computing Using An MDE Approach. [Citation Graph (, )][DBLP]


  47. Visual Data-Parallel Programming for Signal Processing Applications. [Citation Graph (, )][DBLP]


  48. Model Transformations for the Compilation of Multi-processor Systems-on-Chip. [Citation Graph (, )][DBLP]


  49. Safe Design Methodology for an Intelligent Cruise Control System with GPS. [Citation Graph (, )][DBLP]


  50. Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. [Citation Graph (, )][DBLP]


  51. An Open Framework for Detailed Hardware Modeling. [Citation Graph (, )][DBLP]


  52. MARTE-based Design of a Multimedia Application and Formal Analysis. [Citation Graph (, )][DBLP]


  53. UML2 Profile for Modeling Controlled Data Parallel Applications. [Citation Graph (, )][DBLP]


  54. Model Transformations from a Data Parallel Formalism towards Synchronous Languages. [Citation Graph (, )][DBLP]


  55. MARTE: UML-based Hardware Design from Modelling to Simulation. [Citation Graph (, )][DBLP]


  56. Metamodels and MDA Transformations for Embedded Systems. [Citation Graph (, )][DBLP]


  57. Embed Scripting inside SystemC. [Citation Graph (, )][DBLP]


  58. Traceability and Interoperability in Models Transformations. [Citation Graph (, )][DBLP]


  59. Regular Hardware Architecture Modeling with UML2. [Citation Graph (, )][DBLP]


  60. MDA for SoC Design, Intensive Signal Processing Experiment. [Citation Graph (, )][DBLP]


  61. An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). [Citation Graph (, )][DBLP]


  62. MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. [Citation Graph (, )][DBLP]


  63. Interoperability between Design and Simulation Tools using Model Transformation Techniques. [Citation Graph (, )][DBLP]


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