Search the dblp DataBase
Hamid R. Arabnia :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Hamid R. Arabnia , Xiangjian He Scalable Switch for Uni-Directional MultiRing Network. [Citation Graph (0, 0)][DBLP ] ISCA PDCS, 2004, pp:302-307 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture. [Citation Graph (0, 0)][DBLP ] AMCS, 2005, pp:72-76 [Conf ] Valery V. Gritsak-Groener , Julia Gritsak-Groener , Hamid R. Arabnia Algorithms for Computational Viral Extension - Direct and Inverse Problems. [Citation Graph (0, 0)][DBLP ] BIOCOMP, 2006, pp:434-444 [Conf ] Himanshu Thapliyal , A. Rameshwar , Rajnish Bajpai , Hamid R. Arabnia Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations. [Citation Graph (0, 0)][DBLP ] CDES, 2006, pp:130-134 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Design for A Fast And Low Power 2's Complement Multiplier. [Citation Graph (0, 0)][DBLP ] CDES, 2005, pp:165-167 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Rameshwar Rao , Hamid R. Arabnia Verilog Coding Style for Efficient Synthesis In FPGA. [Citation Graph (0, 0)][DBLP ] CDES, 2005, pp:85-90 [Conf ] Himanshu Thapliyal , Vishal Verma , Hamid R. Arabnia A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs. [Citation Graph (0, 0)][DBLP ] CDES, 2006, pp:36-38 [Conf ] Himanshu Thapliyal , Hamid R. Arabnia Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation. [Citation Graph (0, 0)][DBLP ] CDES, 2006, pp:64-69 [Conf ] Himanshu Thapliyal , Hamid R. Arabnia A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications. [Citation Graph (0, 0)][DBLP ] CDES, 2006, pp:70-76 [Conf ] M. Arif Wani , Hamid R. Arabnia Parallel Polygon Approximation Algorithm Targeted at Reconfigurable Multi-Ring Hardware. [Citation Graph (0, 0)][DBLP ] CGVR, 2006, pp:86-96 [Conf ] Shrirang M. Yardi , Hamid R. Arabnia A Communication Framework for the Reconfigurable Multi-Ring Network. [Citation Graph (0, 0)][DBLP ] Communications in Computing, 2003, pp:47-57 [Conf ] Felicia S. Jones , Hamid R. Arabnia Automatic Region Growing Algorithm for the Visible Human Dateset. [Citation Graph (0, 0)][DBLP ] CISST, 2003, pp:665-672 [Conf ] Ananda S. Chowdhury , Hamid R. Arabnia A Comprehensive Study of Stereo Correlation Performance. [Citation Graph (0, 0)][DBLP ] CISST, 2004, pp:411-420 [Conf ] Matthias Wiemann , Hamid R. Arabnia Stereo Images and Genetic Algorithms: Making Computers See Depth. [Citation Graph (0, 0)][DBLP ] CISST, 2004, pp:501-520 [Conf ] Valery V. Gritsak-Groener , Julia Gritsak-Groener , Hamid R. Arabnia Superpower Computational Creation for Biological Computing. [Citation Graph (0, 0)][DBLP ] CSC, 2005, pp:184-190 [Conf ] Saurabh Kotiyal , Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. [Citation Graph (0, 0)][DBLP ] CSC, 2005, pp:74-77 [Conf ] Hamid R. Arabnia , Julia Gritsak-Groener , Valery V. Gritsak-Groener Biological Computing. [Citation Graph (0, 0)][DBLP ] CSC, 2006, pp:284-292 [Conf ] Himanshu Thapliyal , Hamid R. Arabnia High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP ] ESA/VLSI, 2004, pp:413-416 [Conf ] Himanshu Thapliyal , Hamid R. Arabnia A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP ] ESA/VLSI, 2004, pp:434-439 [Conf ] Himanshu Thapliyal , Hamid R. Arabnia A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP ] ESA/VLSI, 2004, pp:440-446 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor. [Citation Graph (0, 0)][DBLP ] ESA, 2005, pp:60-68 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs. [Citation Graph (0, 0)][DBLP ] ESA, 2005, pp:106-116 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Reversible Logic Synthesis of Half, Full and Parallel Subtractors. [Citation Graph (0, 0)][DBLP ] ESA, 2005, pp:165-181 [Conf ] Pallavi Devi Gopineedi , Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. [Citation Graph (0, 0)][DBLP ] ESA, 2006, pp:160-168 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier. [Citation Graph (0, 0)][DBLP ] Security and Management, 2005, pp:40-44 [Conf ] Himanshu Thapliyal , M. B. Srinivas , Hamid R. Arabnia Implementation of A Fast Square In RSA Encryption/Decryption Architecture. [Citation Graph (0, 0)][DBLP ] Security and Management, 2005, pp:371-374 [Conf ] Junfeng Qu , Hamid R. Arabnia Mining Structural Changes in Financial Time Series with Gray System. [Citation Graph (0, 0)][DBLP ] DMIN, 2005, pp:173-180 [Conf ] Hamid R. Arabnia A distributed stereocorrelation algorithm. [Citation Graph (0, 0)][DBLP ] ICCCN, 1995, pp:479- [Conf ] Hamid R. Arabnia A Multi-Ring Transputer Network for the Arbitrary Rotation of Raster Images. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1990, pp:591-592 [Conf ] Hamid R. Arabnia Towards a General-Purpose Parallel System for Imaging Operations. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1991, pp:644-645 [Conf ] Suchendra M. Bhandarkar , Hamid R. Arabnia A Novel Reconfigurable Multiprocessor for Robot Vision. [Citation Graph (0, 0)][DBLP ] ICRA, 1994, pp:2857-2862 [Conf ] Junfeng Qu , Hamid R. Arabnia A novel short-term stock price predicting system. [Citation Graph (0, 0)][DBLP ] IKE, 2005, pp:25-31 [Conf ] Hamid R. Arabnia High-Performance Computing and Applications in Image Processing and Computer Vision. [Citation Graph (0, 0)][DBLP ] ISHPC, 1997, pp:72- [Conf ] Rabia Jafri , Hamid R. Arabnia Analysis of Subspace-based Face Recognition Techniques under Changes in Imaging Factors. [Citation Graph (0, 0)][DBLP ] ITNG, 2007, pp:406-413 [Conf ] Valery V. Gritsak-Groener , Julia Gritsak-Groener , Hamid R. Arabnia A Microscope Algorithm and Its Applications in Calculation of Chemical Preparations with Antiviral Effects. [Citation Graph (0, 0)][DBLP ] METMBS, 2005, pp:307-314 [Conf ] Durga Yeluri , Hamid R. Arabnia , Steven Budsberg , Guigen Zhang Using Pattern Recognition Techniques in the Gait Analysis to Determine Osteoarthritis in Dogs. [Citation Graph (0, 0)][DBLP ] METMBS, 2004, pp:503-511 [Conf ] Hamid R. Arabnia , Xiangjian He Edge Detection Using MultiRing on Spiral Architecture. [Citation Graph (0, 0)][DBLP ] PDPTA, 2004, pp:413-419 [Conf ] Hamid R. Arabnia , Jeffrey W. Smith Emulation of a Parallel System Interconnection Network Implemented with Sockets. [Citation Graph (0, 0)][DBLP ] PDPTA, 1996, pp:561-564 [Conf ] Xiangjian He , Hamid R. Arabnia Parallel Edge Detection Using Uni-Directional MultiRing on Spiral Architecture. [Citation Graph (0, 0)][DBLP ] PDPTA, 2004, pp:420-428 [Conf ] Leonidas Deligiannidis , Hamid R. Arabnia MRSIM: A Simulator for the MultiRing. [Citation Graph (0, 0)][DBLP ] PDPTA, 2005, pp:571-577 [Conf ] Ananda S. Chowdhury , Hamid R. Arabnia , Dipankar Bandyopadhyay Improved Stereo Correlation using Moravec Operator and Kolmogorov-Smirnov Test. [Citation Graph (0, 0)][DBLP ] VISION, 2005, pp:24-32 [Conf ] Hamid R. Arabnia , M. A. Oliver Arbitrary Rotation of Raster Images with SIMD Machine Architectures. [Citation Graph (0, 0)][DBLP ] Comput. Graph. Forum, 1987, v:6, n:1, pp:3-11 [Journal ] Hamid R. Arabnia , M. A. Oliver A Transputer Network for Fast Operations on Digitised Images. [Citation Graph (0, 0)][DBLP ] Comput. Graph. Forum, 1989, v:8, n:1, pp:3-11 [Journal ] Hamid R. Arabnia , M. A. Oliver A Transputer Network for the Arbitrary Rotation of Digitised Images. [Citation Graph (0, 0)][DBLP ] Comput. J., 1987, v:30, n:5, pp:425-432 [Journal ] Hamid R. Arabnia Distributed stereo-correlation algorithm. [Citation Graph (0, 0)][DBLP ] Computer Communications, 1996, v:19, n:8, pp:707-711 [Journal ] George A. Gravvanis , Hamid R. Arabnia Special section: Parallel and distributed algorithms and systems. [Citation Graph (0, 0)][DBLP ] Future Generation Comp. Syst., 2006, v:22, n:1-2, pp:32-33 [Journal ] George A. Gravvanis , John P. Morrison , Hamid R. Arabnia Special section: Grid technology and applications. [Citation Graph (0, 0)][DBLP ] Future Generation Comp. Syst., 2007, v:23, n:4, pp:523-524 [Journal ] Kai Wang , Chor-Pang Lo , George A. Brook , Hamid R. Arabnia Comparison of existing triangulation methods for regularly and irregularly spaced height fields. [Citation Graph (0, 0)][DBLP ] International Journal of Geographical Information Science, 2001, v:15, n:8, pp:743-762 [Journal ] Robert A. Gougher , Hamid R. Arabnia Media Reviews. [Citation Graph (0, 0)][DBLP ] IEEE MultiMedia, 1999, v:6, n:4, pp:91-93 [Journal ] Suchendra M. Bhandarkar , Hamid R. Arabnia , Jeffrey W. Smith A Reconfigurable Architecture for Image Processing and Computer Vision. [Citation Graph (0, 0)][DBLP ] IJPRAI, 1995, v:9, n:2, pp:201-229 [Journal ] Hamid R. Arabnia , Keqin Li Guest Editorial. [Citation Graph (0, 0)][DBLP ] Inf. Sci., 1998, v:106, n:3-4, pp:197-199 [Journal ] Hamid R. Arabnia , George A. Gravvanis Editorial - Special Issue: Computational Sciences and Applications. [Citation Graph (0, 0)][DBLP ] J. Math. Model. Algorithms, 2003, v:2, n:3, pp:183-184 [Journal ] Hamid R. Arabnia A Parallel Algorithm for the Arbitrary Rotation of Digitized Images Using Process-and-Data-Decomposition Approach. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 1990, v:10, n:2, pp:188-192 [Journal ] Suchendra M. Bhandarkar , Hamid R. Arabnia The Hough Transform on a Reconfigurable Multi-Ring Network. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 1995, v:24, n:1, pp:107-114 [Journal ] George A. Gravvanis , Hamid R. Arabnia The Journal of Parallel Algorithms and Applications: Special Issue on Parallel and Distributed Algorithms. [Citation Graph (0, 0)][DBLP ] Parallel Algorithms Appl., 2004, v:19, n:2-3, pp:77-78 [Journal ] Suchendra M. Bhandarkar , Hamid R. Arabnia The REFINE Multiprocessor - Theoretical Properties and Algorithms. [Citation Graph (0, 0)][DBLP ] Parallel Computing, 1995, v:21, n:11, pp:1783-1805 [Journal ] Hamid R. Arabnia , Thiab R. Taha A parallel numerical algorithm on a reconfigurable multi-ring network. [Citation Graph (0, 0)][DBLP ] Telecommunication Systems, 1998, v:10, n:1, pp:185-202 [Journal ] Hamid R. Arabnia Editorial. [Citation Graph (0, 0)][DBLP ] The Journal of Supercomputing, 1998, v:12, n:1-2, pp:5-6 [Journal ] M. Arif Wani , Hamid R. Arabnia Parallel Edge-Region-Based Segmentation Algorithm Targeted at Reconfigurable MultiRing Network. [Citation Graph (0, 0)][DBLP ] The Journal of Supercomputing, 2003, v:25, n:1, pp:43-62 [Journal ] Suchendra M. Bhandarkar , Hamid R. Arabnia Parallel Computer Vision on a Reconfigurable Multiprocessor Network. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:3, pp:292-309 [Journal ] Himanshu Thapliyal , Hamid R. Arabnia , A. Prasad Vinod Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Himanshu Thapliyal , Hamid R. Arabnia Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Himanshu Thapliyal , Hamid R. Arabnia , M. B. Srinivas Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format [Citation Graph (0, 0)][DBLP ] CoRR, 2006, v:0, n:, pp:- [Journal ] Partial Reversible Gates(PRG) for Reversible BCD Arithmetic. [Citation Graph (, )][DBLP ] PCA-Based Methods for Face Recognition. [Citation Graph (, )][DBLP ] An Integrated Face-Gait System for Automatic Recognition of Humans. [Citation Graph (, )][DBLP ] A Scalable Network Topology for Medical Imaging. [Citation Graph (, )][DBLP ] A Survey of Component-Based Face Recognition Approaches. [Citation Graph (, )][DBLP ] Path Normalcy Analysis Using Nearest Neighbor Outlier Detection. [Citation Graph (, )][DBLP ] A Multi-Resolution Hierarchical Approach for Face Recognition. [Citation Graph (, )][DBLP ] Spatial and Temporal Target Association through Semantic Analysis and GPS Data Mining. [Citation Graph (, )][DBLP ] Time Series Similarity Matching with a New Distance Measure. [Citation Graph (, )][DBLP ] Knowledge Retrieval in Financial Domain. [Citation Graph (, )][DBLP ] Positional Forecasting From Logged Training Data Using Probabilistic Neural Networks. [Citation Graph (, )][DBLP ] PaperGuard: A Support Vector Machine Approach for Screening Machine Generated Papers. [Citation Graph (, )][DBLP ] Fusion of Face and Gait for Automatic Human Recognition. [Citation Graph (, )][DBLP ] Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs. [Citation Graph (, )][DBLP ] High Performance Computing and Computational Intelligence: Link to the Translational Medicine and Personalized Healthcare - Banquet Keynote Lecture. [Citation Graph (, )][DBLP ] The Impact of Supercomputing in the Next Generation Sequencing Data Mining. [Citation Graph (, )][DBLP ] Parallel Stereocorrelation with Applications in Medical Imaging. [Citation Graph (, )][DBLP ] A Reconfigurable Ring-Based Network of Processors. [Citation Graph (, )][DBLP ] A Multi-Level Component-Based Approach for Face Recognition. [Citation Graph (, )][DBLP ] Comparison of Statistical Based Thresholding Methods for Nanostructure Images. [Citation Graph (, )][DBLP ] Preface. [Citation Graph (, )][DBLP ] Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs [Citation Graph (, )][DBLP ] Partial Reversible Gates(PRG) for Reversible BCD Arithmetic [Citation Graph (, )][DBLP ] Search in 0.042secs, Finished in 0.046secs