The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Meilin Liu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kevin F. Chen, Meilin Liu, Edwin Hsing-Mean Sha
    A Feasible Baseline Architecture for Building and Evaluating Distributed Systems. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2005, pp:185-190 [Conf]
  2. Meilin Liu, Zili Shao, Chun Xue, Kevin F. Chen, Edwin Hsing-Mean Sha
    Multi-level Loop Fusion with Minimal Code Size. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2005, pp:348-0 [Conf]
  3. Meilin Liu, Chun Xue, Edwin Hsing-Mean Sha
    Optimizing Timing and Code Size Using Maximum Direct Loop Fusion. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2006, pp:38-43 [Conf]
  4. Meilin Liu, Qingfeng Zhuge, Zili Shao, Kevin F. Chen, Edwin Hsing-Mean Sha
    Loop Fusion via Retiming for DSP Applications. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2004, pp:403-408 [Conf]
  5. Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
    Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:178-181 [Conf]
  6. Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha
    Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:224-234 [Conf]
  7. Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
    General loop fusion technique for nested loops considering timing and code size. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:190-201 [Conf]
  8. Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
    Iterational retiming: maximize iteration-level parallelism for nested loops. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:309-314 [Conf]
  9. Mei Kang Qiu, Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha
    Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network. [Citation Graph (0, 0)][DBLP]
    EUC, 2006, pp:25-34 [Conf]
  10. Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha
    Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:121-130 [Conf]
  11. Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha, Bin Xiao
    Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures. [Citation Graph (0, 0)][DBLP]
    EUC, 2004, pp:53-63 [Conf]
  12. Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
    Optimizing Nested Loops with Iterational and Instructional Retiming. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:164-173 [Conf]
  13. Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
    Loop Striping: Maximize Parallelism for Nested Loops. [Citation Graph (0, 0)][DBLP]
    EUC, 2006, pp:405-414 [Conf]
  14. Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
    Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2006, pp:375-382 [Conf]
  15. Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha
    Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  16. Mei Kang Qiu, Meilin Liu, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Zili Shao
    Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2005, pp:295-300 [Conf]
  17. Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha
    Design optimization and space minimization considering timing and code size via retiming and unfolding. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:4, pp:173-183 [Journal]

  18. Loop Fusion Technique with Minimal Memory Cost via Retiming. [Citation Graph (, )][DBLP]


  19. Parallel Network Intrusion Detection on Reconfigurable Platforms. [Citation Graph (, )][DBLP]


  20. Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002