The SCEAS System
| |||||||

## Search the dblp DataBase
Edwin Hsing-Mean Sha:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Kevin F. Chen, Meilin Liu, Edwin Hsing-Mean Sha
**A Feasible Baseline Architecture for Building and Evaluating Distributed Systems.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2005, pp:185-190 [Conf] - Kevin F. Chen, Edwin Hsing-Mean Sha
**The Fat-Stack and Universal Routing in Interconnection Networks.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2004, pp:321-326 [Conf] - Meilin Liu, Zili Shao, Chun Xue, Kevin F. Chen, Edwin Hsing-Mean Sha
**Multi-level Loop Fusion with Minimal Code Size.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2005, pp:348-0 [Conf] - Meilin Liu, Chun Xue, Edwin Hsing-Mean Sha
**Optimizing Timing and Code Size Using Maximum Direct Loop Fusion.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2006, pp:38-43 [Conf] - Meilin Liu, Qingfeng Zhuge, Zili Shao, Kevin F. Chen, Edwin Hsing-Mean Sha
**Loop Fusion via Retiming for DSP Applications.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2004, pp:403-408 [Conf] - Bin Xiao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**Design and Analysis of Improved Shortest Path Tree Update for Network Routing.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2003, pp:82-87 [Conf] - Cathy Qun Xu, Youtao Zhang, Edwin Hsing-Mean Sha
**Application-Specific Interconnection Network Design in Clustered DSP Processors.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2003, pp:69-75 [Conf] - Zili Shao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean Sha
**Defending Embedded Systems Against Buffer Overflow via Hardware/Software.**[Citation Graph (0, 0)][DBLP] ACSAC, 2003, pp:352-363 [Conf] - Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
**Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.**[Citation Graph (0, 0)][DBLP] ASAP, 2006, pp:178-181 [Conf] - Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha
**Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.**[Citation Graph (0, 0)][DBLP] ASAP, 2004, pp:224-234 [Conf] - David R. Surma, Edwin Hsing-Mean Sha
**Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems.**[Citation Graph (0, 0)][DBLP] ASAP, 1996, pp:240-249 [Conf] - Chantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha
**Design Exploration Framework Under Impreciseness Based on Register-Constrained Inclusion Scheduling.**[Citation Graph (0, 0)][DBLP] ASIAN, 2004, pp:78-92 [Conf] - Chantana Chantrapornchai, Sissades Tongsima, Edwin Hsing-Mean Sha
**Rapid Prototyping Techniques for Fuzzy Controllers.**[Citation Graph (0, 0)][DBLP] ASIAN, 1999, pp:37-49 [Conf] - Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha
**High-level synthesis for DSP applications using heterogeneous functional units.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:302-304 [Conf] - Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**General loop fusion technique for nested loops considering timing and code size.**[Citation Graph (0, 0)][DBLP] CASES, 2004, pp:190-201 [Conf] - Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu
**Combined partitioning and data padding for scheduling multiple loop nests.**[Citation Graph (0, 0)][DBLP] CASES, 2001, pp:67-75 [Conf] - Michael Sheliga, Nelson L. Passos, Edwin Hsing-Mean Sha
**Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications.**[Citation Graph (0, 0)][DBLP] CODES, 1996, pp:18-27 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
**Iterational retiming: maximize iteration-level parallelism for nested loops.**[Citation Graph (0, 0)][DBLP] CODES+ISSS, 2005, pp:309-314 [Conf] - Tao Zhou, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha
**A probabilistic performance metric for real-time system design.**[Citation Graph (0, 0)][DBLP] CODES, 1999, pp:90-94 [Conf] - Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-Mean Sha
**Design space minimization with timing and code size optimization for embedded DSP.**[Citation Graph (0, 0)][DBLP] CODES+ISSS, 2003, pp:144-149 [Conf] - Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha
**Rotation Scheduling: A Loop Pipelining Algorithm.**[Citation Graph (0, 0)][DBLP] DAC, 1993, pp:566-572 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass
**Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation.**[Citation Graph (0, 0)][DBLP] DAC, 1994, pp:485-490 [Conf] - Zhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha
**Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:540-545 [Conf] - Chantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha
**Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints.**[Citation Graph (0, 0)][DBLP] EUC, 2004, pp:259-270 [Conf] - Mei Kang Qiu, Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha
**Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.**[Citation Graph (0, 0)][DBLP] EUC, 2006, pp:25-34 [Conf] - Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:121-130 [Conf] - Edwin Hsing-Mean Sha
**Parallel Embedded Systems: Optimizations and Challenges.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:2- [Conf] - Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha, Bin Xiao
**Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.**[Citation Graph (0, 0)][DBLP] EUC, 2004, pp:53-63 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Optimizing Nested Loops with Iterational and Instructional Retiming.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:164-173 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Striping: Maximize Parallelism for Nested Loops.**[Citation Graph (0, 0)][DBLP] EUC, 2006, pp:405-414 [Conf] - Chun Xue, Zili Shao, Edwin Hsing-Mean Sha, Bin Xiao
**Optimizing Address Assignment for Scheduling Embedded DSPs.**[Citation Graph (0, 0)][DBLP] EUC, 2004, pp:64-73 [Conf] - Bin Xiao, Jiannong Cao, Edwin Hsing-Mean Sha
**Maintaining Comprehensive Resource Availability in P2P Networks.**[Citation Graph (0, 0)][DBLP] GCC, 2004, pp:543-550 [Conf] - Virgil Andronache, Edwin Hsing-Mean Sha, Nelson L. Passos
**Design and analysis of efficient application-specific on-line page replacement techniques.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:123-128 [Conf] - Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu
**Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1999, pp:128-131 [Conf] - Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Hu
**Efficient algorithms for acceptable design exploration.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:139-142 [Conf] - Chantana Chantrapornchai, Sissades Tongsima, Edwin Hsing-Mean Sha
**Rapid Prototyping for Fuzzy Systems.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1996, pp:234-239 [Conf] - Timothy W. O'Neil, Edwin Hsing-Mean Sha
**Minimizing resources in a repeating schedule for a split-node data-flow graph.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2002, pp:136-141 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha
**A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1996, pp:66-71 [Conf] - Michael Sheliga, Edwin Hsing-Mean Sha
**Bus minimization and scheduling of multi-chip systems.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1995, pp:40-45 [Conf] - Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos
**Scheduling with Confidence for Probabilistic Data-flow Graphs.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1997, pp:150-155 [Conf] - Zhong Wang, Edwin Hsing-Mean Sha, Yuke Wang
**Optimal partitioning and balanced scheduling with the maximal overlap of data footprints.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2001, pp:31-36 [Conf] - Kaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha
**RCRS: A Framework for Loop Scheduling with Limited Number of Registers.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1998, pp:386-391 [Conf] - Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Passos, Roy Dz-Ching Ju
**Algorithm and Hardware Support for Branch Anticipation.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1997, pp:163-0 [Conf] - Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha
**Improving self-timed pipeline ring performance through the addition of buffer loops.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1995, pp:218-223 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha
**Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications.**[Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:588-591 [Conf] - Edwin Hsing-Mean Sha, Liang-Fang Chao
**Design for Easily Applying Test Vectors to Improve Delay Fault Coverage.**[Citation Graph (0, 0)][DBLP] ICCAD, 1991, pp:500-503 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao
**Multi-dimensional interleaving for time-and-memory design optimization.**[Citation Graph (0, 0)][DBLP] ICCD, 1995, pp:440-445 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha
**Synthesis of Multi-Dimensional Applications in VHDL.**[Citation Graph (0, 0)][DBLP] ICCD, 1996, pp:530-0 [Conf] - Sissades Tongsima, Nelson L. Passos, Edwin Hsing-Mean Sha
**Communication Sensitive Rotation Scheduling.**[Citation Graph (0, 0)][DBLP] ICCD, 1994, pp:150-153 [Conf] - Kevin F. Chen, Edwin Hsing-Mean Sha, Bin Xiao
**Universal Routing in Distributed Networks.**[Citation Graph (0, 0)][DBLP] ICPADS (2), 2005, pp:555-559 [Conf] - Ying Chen, Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha
**Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems.**[Citation Graph (0, 0)][DBLP] ICPADS (2), 2005, pp:2-6 [Conf] - Bin Xiao, Wei Chen, Yanxiang He, Edwin Hsing-Mean Sha
**An Active Detecting Method Against SYN Flooding Attack.**[Citation Graph (0, 0)][DBLP] ICPADS (1), 2005, pp:709-715 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.**[Citation Graph (0, 0)][DBLP] ICPADS (1), 2006, pp:375-382 [Conf] - Liang-Fang Chao, Edwin Hsing-Mean Sha
**Retiming and Unfolding Data-Flow Graphs.**[Citation Graph (0, 0)][DBLP] ICPP (2), 1992, pp:33-40 [Conf] - Liang-Fang Chao, Edwin Hsing-Mean Sha
**Unified Static Scheduling on Various Models.**[Citation Graph (0, 0)][DBLP] ICPP, 1993, pp:231-235 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha
**Full Parallelism in Uniform Nested Loops Using Multi-Dimensional Retiming.**[Citation Graph (0, 0)][DBLP] ICPP, 1994, pp:130-133 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao
**Memory Efficient Fully Parallel Nested Loop Pipelining.**[Citation Graph (0, 0)][DBLP] ICPP (2), 1995, pp:182-185 [Conf] - Edwin Hsing-Mean Sha, Chenhua Lang, Nelson L. Passos
**Polynomial-Time Nested Loop Fusion with Full Parallelism.**[Citation Graph (0, 0)][DBLP] ICPP, Vol. 3, 1996, pp:9-16 [Conf] - Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos
**Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time.**[Citation Graph (0, 0)][DBLP] ICPP, 1997, pp:292-0 [Conf] - Sissades Tongsima, Nelson L. Passos, Edwin Hsing-Mean Sha
**Architecture-Dependent Loop Scheduling via Communication-Sensitive Remapping.**[Citation Graph (0, 0)][DBLP] ICPP (2), 1995, pp:97-104 [Conf] - Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications.**[Citation Graph (0, 0)][DBLP] ICPP, 2002, pp:613-620 [Conf] - Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**Timing Optimization of Nested Loops Considering Code Size for DSP Applications.**[Citation Graph (0, 0)][DBLP] ICPP, 2004, pp:475-482 [Conf] - Liang-Fang Chao, Edwin Hsing-Mean Sha
**Static Scheduling of Uniform Nested Loops.**[Citation Graph (0, 0)][DBLP] IPPS, 1993, pp:254-258 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass
**Schedule-Based Multi-Dimensional Retiming on Data Flow Graphs.**[Citation Graph (0, 0)][DBLP] IPPS, 1994, pp:195-199 [Conf] - Edwin Hsing-Mean Sha, Kenneth Steiglitz
**Maintaining Bipartite Matchings in the Presence of Failures.**[Citation Graph (0, 0)][DBLP] IPPS, 1993, pp:57-64 [Conf] - Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha
**Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.**[Citation Graph (0, 0)][DBLP] IPDPS, 2004, pp:- [Conf] - Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, Peter M. Kogge
**Optimizing Data Scheduling on Processor-in-Memory Arrays.**[Citation Graph (0, 0)][DBLP] IPPS/SPDP, 1998, pp:57-61 [Conf] - Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
**Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP.**[Citation Graph (0, 0)][DBLP] IPDPS, 2002, pp:- [Conf] - Liang-Fang Chao, Edwin Hsing-Mean Sha
**Retiming and Clock Skew for Synchronous Systems.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:283-286 [Conf] - Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass
**Partitioning and Retiming of Multi-Dimensional Systems.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:227-230 [Conf] - Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai
**Loop scheduling for minimizing schedule length and switching activities.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:109-112 [Conf] - Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai
**An Integrated Framework of Design Optimization and Space Minimization for DSP applications.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:601-604 [Conf] - Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
**Performance optimization of multiple memory architectures for DSP.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2002, pp:469-472 [Conf] - Bin Xiao, Jiannong Cao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean Sha
**Approximation Algorithms Design for Disk Partial Covering Problem.**[Citation Graph (0, 0)][DBLP] ISPAN, 2004, pp:104-110 [Conf] - Bin Xiao, Jiannong Cao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**Dynamic Update of Shortest Path Tree in OSPF.**[Citation Graph (0, 0)][DBLP] ISPAN, 2004, pp:18-23 [Conf] - Fei Chen, Edwin Hsing-Mean Sha
**Loop Scheduling and Partitions for Hiding Memory Latencies.**[Citation Graph (0, 0)][DBLP] ISSS, 1999, pp:64-70 [Conf] - Zhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha
**Scheduling and partitioning for multiple loop nests.**[Citation Graph (0, 0)][DBLP] ISSS, 2001, pp:183-188 [Conf] - Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge
**Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.**[Citation Graph (0, 0)][DBLP] ISSS, 2002, pp:144-149 [Conf] - Jiangfeng Ding, Jon C. Furgeson, Edwin Hsing-Mean Sha
**Application Specific Image Compression for Virtual Conferencing.**[Citation Graph (0, 0)][DBLP] ITCC, 2000, pp:48-53 [Conf] - Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao
**Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks.**[Citation Graph (0, 0)][DBLP] ITCC (1), 2004, pp:409-413 [Conf] - Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao
**Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software.**[Citation Graph (0, 0)][DBLP] ITCC (1), 2005, pp:780-785 [Conf] - Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha
**Probabilistic Loop Scheduling Considering Communication Overhead.**[Citation Graph (0, 0)][DBLP] JSSPP, 1998, pp:158-179 [Conf] - Timothy W. O'Neil, Edwin Hsing-Mean Sha
**Unfolding a Split-node Data-flow Graph.**[Citation Graph (0, 0)][DBLP] IASTED PDCS, 2002, pp:712-717 [Conf] - Timothy W. O'Neil, Edwin Hsing-Mean Sha
**Static Scheduling of Split-Node Data-Flow Graphs.**[Citation Graph (0, 0)][DBLP] IASTED PDCS, 2005, pp:125-130 [Conf] - Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai
**Analysis and Algorithms for Partitioning of Large-scale Adaptive Mobile Networks.**[Citation Graph (0, 0)][DBLP] IASTED PDCS, 2002, pp:302-308 [Conf] - Mei Kang Qiu, Meilin Liu, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Zili Shao
**Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.**[Citation Graph (0, 0)][DBLP] IASTED PDCS, 2005, pp:295-300 [Conf] - David R. Surma, Edwin Hsing-Mean Sha
**Hybrid static-dynamic communication scheduling for parallel systems.**[Citation Graph (0, 0)][DBLP] SAC, 1997, pp:374-379 [Conf] - Edwin Hsing-Mean Sha, Timothy W. O'Neil, Nelson L. Passos
**Efficient Polynomial-Time Nested Loop Fusion with Full Parallelism.**[Citation Graph (0, 0)][DBLP] I. J. Comput. Appl., 2003, v:10, n:1, pp:9-24 [Journal] - Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha
**Efficient Algorithms for Dynamic Update of Shortest Path Tree in Networking.**[Citation Graph (0, 0)][DBLP] I. J. Comput. Appl., 2004, v:11, n:1, pp:60-75 [Journal] - David R. Surma, Edwin Hsing-Mean Sha, Nelson L. Passos
**Communication Scheduling With Re-Routing Based On Static And Hybrid Techniques.**[Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2004, v:13, n:5, pp:1039-1064 [Journal] - Kevin F. Chen, Edwin Hsing-Mean Sha
**The fat-stack and universal routing in interconnection networks.**[Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 2006, v:66, n:5, pp:705-715 [Journal] - Zili Shao, Jiannong Cao, Keith C. C. Chan, Chun Xue, Edwin Hsing-Mean Sha
**Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks.**[Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 2006, v:66, n:9, pp:1129-1136 [Journal] - Edwin Hsing-Mean Sha, Kenneth Steiglitz
**Reconfigurability and Reliability of Systolic/Wavefront Arrays.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1993, v:42, n:7, pp:854-862 [Journal] - Zili Shao, Chun Xue, Qingfeng Zhuge, Mei Kang Qiu, Bin Xiao, Edwin Hsing-Mean Sha
**Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2006, v:55, n:4, pp:443-453 [Journal] - Sissades Tongsima, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, David R. Surma, Nelson L. Passos
**Probabilistic Loop Scheduling for Applications with Uncertain Execution Time.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2000, v:49, n:1, pp:65-80 [Journal] - Qingyan Wang, Nelson L. Passos, Edwin Hsing-Mean Sha
**Optimal Data Scheduling for Uniform Multidimensional Applications.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1996, v:45, n:12, pp:1439-1444 [Journal] - Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu
**Efficient design exploration based on module utility selection.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:19-29 [Journal] - Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha
**Rotation scheduling: a loop pipelining algorithm.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:229-239 [Journal] - Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao
**Multidimensional interleaving for synchronous circuit design optimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:2, pp:146-159 [Journal] - Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
**Code size reduction technique and implementation for software-pipelined DSP applications.**[Citation Graph (0, 0)][DBLP] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:4, pp:590-613 [Journal] - Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha
**Loop scheduling with timing and switching-activity minimization for VLIW DSP.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:165-185 [Journal] - Liang-Fang Chao, Edwin Hsing-Mean Sha
**Scheduling Data-Flow Graphs via Retiming and Unfolding.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:12, pp:1259-1267 [Journal] - Fei Chen, Timothy W. O'Neil, Edwin Hsing-Mean Sha
**Optimizing Overall Loop Schedules Using Prefetching and Partitioning.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:6, pp:604-614 [Journal] - Nelson L. Passos, Edwin Hsing-Mean Sha
**Achieving Full Parallelism Using Multidimensional Retiming.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:11, pp:1150-1163 [Journal] - Zili Shao, Qingfeng Zhuge, Chun Xue, Edwin Hsing-Mean Sha
**Efficient Assignment and Scheduling for Heterogeneous DSP Systems.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:6, pp:516-525 [Journal] - David R. Surma, Edwin Hsing-Mean Sha
**Communication Reduction in Multiple Multicasts Based on Hybrid Static-Dynamic Scheduling.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:9, pp:865-878 [Journal] - Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha
**Design optimization and space minimization considering timing and code size via retiming and unfolding.**[Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2006, v:30, n:4, pp:173-183 [Journal] - Yingtao Jiang, Yuke Wang, Edwin Hsing-Mean Sha
**Distributed Scaling Algorithm for FFT Computation Using Fixed-Point Arithmetic.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2001, pp:490-495 [Conf] - Timothy W. O'Neil, Edwin Hsing-Mean Sha
**On Retiming Synchronous Data-Flow Graphs.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2001, pp:103-108 [Conf] - Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha
**Efficient Update of Shortest Path Algorithms for Network Routing.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2001, pp:315-320 [Conf] - Meikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1641-1646 [Conf] - Meikang Qiu, Edwin Hsing-Mean Sha
**Energy-Aware Online Algorithm to Satisfy Sampling Rates with Guaranteed Probability for Sensor Applications.**[Citation Graph (0, 0)][DBLP] HPCC, 2007, pp:156-167 [Conf] - Meng Wang, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha
**Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.**[Citation Graph (0, 0)][DBLP] RTCSA, 2007, pp:12-19 [Conf] - Bin Xiao, Jiannong Cao, Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha
**Analysis and algorithms design for the partition of large-scale adaptive mobile wireless networks.**[Citation Graph (0, 0)][DBLP] Computer Communications, 2007, v:30, n:8, pp:1899-1912 [Journal] - Anantha Chandrakasan, Edwin Hsing-Mean Sha
**Special Section on Low-Power Electronics and Design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:518-519 [Journal] - Nelson L. Passos, Edwin Hsing-Mean Sha
**Scheduling of uniform multidimensional systems under resource constraints.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:719-730 [Journal] - Xiaobo Sharon Hu, Tao Zhou, Edwin Hsing-Mean Sha
**Estimating probabilistic timing performance for real-time embedded systems.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:833-844 [Journal] - Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2007, v:46, n:1, pp:55-73 [Journal] - Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2007, v:47, n:2, pp:153-167 [Journal] **QoS for Networked Heterogeneous Real-Time Embedded Systems.**[Citation Graph (, )][DBLP]**Computation and data transfer co-scheduling for interconnection bus minimization.**[Citation Graph (, )][DBLP]**Loop Fusion Technique with Minimal Memory Cost via Retiming.**[Citation Graph (, )][DBLP]**ILP optimal scheduling for multi-module memory.**[Citation Graph (, )][DBLP]**Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation.**[Citation Graph (, )][DBLP]**Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints.**[Citation Graph (, )][DBLP]**Parallel Network Intrusion Detection on Reconfigurable Platforms.**[Citation Graph (, )][DBLP]**Applying Situation Awareness to Mobile Proactive Information Delivery.**[Citation Graph (, )][DBLP]**Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment.**[Citation Graph (, )][DBLP]**Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory.**[Citation Graph (, )][DBLP]**Write activity reduction on flash main memory via smart victim cache.**[Citation Graph (, )][DBLP]**Joint Sleep Scheduling and Mode Assignment in Wireless Cyber-Physical Systems.**[Citation Graph (, )][DBLP]**Global Variable Partition with Virtually Shared Scratch Pad Memory to Minimize Schedule Length.**[Citation Graph (, )][DBLP]**A Fast Noniterative Scheduler for Input-Queued Switches with Unbuffered Crossbars.**[Citation Graph (, )][DBLP]**Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.**[Citation Graph (, )][DBLP]**Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems.**[Citation Graph (, )][DBLP]**Heterogeneous real-time embedded software optimization considering hardware platform.**[Citation Graph (, )][DBLP]**Explicit construction for reliable reconfigurable array architectures.**[Citation Graph (, )][DBLP]**Minimizing Transferred Data for Code Update on Wireless Sensor Network.**[Citation Graph (, )][DBLP]**Failure Rate Minimization with Multiple Function Unit Scheduling for Heterogeneous WSNs.**[Citation Graph (, )][DBLP]**Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC.**[Citation Graph (, )][DBLP]**Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.**[Citation Graph (, )][DBLP]**Fast and noniterative scheduling in input-queued switches: Supporting QoS.**[Citation Graph (, )][DBLP]
Search in 0.215secs, Finished in 0.223secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |