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Saraju P. Mohanty: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wentong Li, Saraju P. Mohanty, Krishna M. Kavi
    A Hardware Assisted High Performance PHK Memory Manager. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2006, pp:229-234 [Conf]
  2. Saraju P. Mohanty, Renuka Kumara C., Sridhara Nayak
    FPGA Based Implementation of an Invisible-Robust Image Watermarking Encoder. [Citation Graph (0, 0)][DBLP]
    CIT, 2004, pp:344-353 [Conf]
  3. Cheryl A. Kincaid, Saraju P. Mohanty, Armin R. Mikler, Elias Kougianos, Brandon Parker
    A High Performance ASIC for Cellular Automata (CA) Applications. [Citation Graph (0, 0)][DBLP]
    ICIT, 2006, pp:289-290 [Conf]
  4. Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos
    Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1191-1196 [Conf]
  5. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    Simultaneous peak and average power minimization during datapath scheduling for DSP processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:215-220 [Conf]
  6. Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos
    A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:431-437 [Conf]
  7. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:441-443 [Conf]
  8. Saraju P. Mohanty, K. R. Ramakrishnan, Mohan S. Kankanhalli
    A DCT Domain Visible Watermarking Technique for Images. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (II), 2000, pp:1029-1032 [Conf]
  9. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:313-316 [Conf]
  10. Saraju P. Mohanty, Guturu Parthasarathy, Elias Kougianos, Nishikanta Pati
    A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction. [Citation Graph (0, 0)][DBLP]
    ISM, 2006, pp:153-160 [Conf]
  11. Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos
    Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:564-569 [Conf]
  12. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    Peak Power Minimization Through Datapath Scheduling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:121-126 [Conf]
  13. Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna
    Datapath Scheduling using Dynamic Frequency Clocking. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:65-70 [Conf]
  14. Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki Mukherjee, Hao Li
    Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:248-249 [Conf]
  15. Saraju P. Mohanty, K. R. Ramakrishnan, Mohan S. Kankanhalli
    A dual watermarking technique for images. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia (2), 1999, pp:49-51 [Conf]
  16. Naga M. Kosaraju, Murali Varanasi, Saraju P. Mohanty
    A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:481-484 [Conf]
  17. Saraju P. Mohanty, Elias Kougianos
    Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:83-88 [Conf]
  18. Saraju P. Mohanty, N. Ranganathan
    Energy Efficient Scheduling for Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:446-451 [Conf]
  19. Saraju P. Mohanty, N. Ranganathan
    A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:539-545 [Conf]
  20. Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan
    Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:153-158 [Conf]
  21. Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi
    ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:745-748 [Conf]
  22. Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
    VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1063-0 [Conf]
  23. Saraju P. Mohanty, Elias Kougianos
    Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:577-582 [Conf]
  24. Elias Kougianos, Saraju P. Mohanty
    Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:195-200 [Conf]
  25. Saraju P. Mohanty, N. Ranganathan
    Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:330-353 [Journal]
  26. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    ILP models for simultaneous energy and transient power minimization during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:186-212 [Journal]
  27. Saraju P. Mohanty, Nagarajan Ranganathan
    A framework for energy and transient power reduction during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:562-572 [Journal]
  28. Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
    A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:808-818 [Journal]
  29. Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
    A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:1002-1012 [Journal]
  30. Yue Zhuo, Hao Li, Saraju P. Mohanty
    A Congestion Driven Placement Algorithm for FPGA Synthesis. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  31. Elias Kougianos, Saraju P. Mohanty
    Effective tunneling capacitance: a new metric to quantify transient gate leakage current. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  32. Saraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee
    Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  33. IntellBatt: towards smarter battery design. [Citation Graph (, )][DBLP]


  34. Single ended 6T SRAM with isolated read-port for low-power embedded systems. [Citation Graph (, )][DBLP]


  35. A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. [Citation Graph (, )][DBLP]


  36. Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. [Citation Graph (, )][DBLP]


  37. Low power nanoscale buffer management for network on chip routers. [Citation Graph (, )][DBLP]


  38. A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. [Citation Graph (, )][DBLP]


  39. Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates. [Citation Graph (, )][DBLP]


  40. A nano-CMOS process variation induced read failure tolerant SRAM cell. [Citation Graph (, )][DBLP]


  41. A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs. [Citation Graph (, )][DBLP]


  42. ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis. [Citation Graph (, )][DBLP]


  43. Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. [Citation Graph (, )][DBLP]


  44. VLSI architectures of perceptual based video watermarking for real-time copyright protection. [Citation Graph (, )][DBLP]


  45. Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. [Citation Graph (, )][DBLP]


  46. A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. [Citation Graph (, )][DBLP]


  47. A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. [Citation Graph (, )][DBLP]


  48. A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. [Citation Graph (, )][DBLP]


  49. On the design of different concurrent EDC schemes for S-Box and GF(p). [Citation Graph (, )][DBLP]


  50. P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP. [Citation Graph (, )][DBLP]


  51. Layout-aware Illinois Scan design for high fault coverage coverage. [Citation Graph (, )][DBLP]


  52. Unified Challenges in Nano-CMOS High-Level Synthesis. [Citation Graph (, )][DBLP]


  53. Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. [Citation Graph (, )][DBLP]


  54. A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO. [Citation Graph (, )][DBLP]


  55. A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. [Citation Graph (, )][DBLP]


  56. A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. [Citation Graph (, )][DBLP]


  57. Failure analysis for ultra low power nano-CMOS SRAM under process variations. [Citation Graph (, )][DBLP]


  58. A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator. [Citation Graph (, )][DBLP]


  59. IntellBatt: Toward a Smarter Battery. [Citation Graph (, )][DBLP]


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