Search the dblp DataBase

Publications of Author

1. René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino
   On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification. [Citation Graph (0, 0)][DBLP]
   CIARP, 2006, pp:665-673 [Conf]
   
2. Tomás Balderas-Contreras, René Cumplido
   High performance encryption cores for 3G networks. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:240-243 [Conf]
   
3. Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido
   Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. [Citation Graph (0, 0)][DBLP]
   ICCSA (3), 2006, pp:456-465 [Conf]
   
4. 
   A UML 2.0 Profile to Model Block Cipher Algorithms. [Citation Graph (, )][DBLP]
   
   
5. 
   FPGA-architecture for Knowledge-Based Target Detection in Radar Signal Processing. [Citation Graph (, )][DBLP]
   
   
6. 
   A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. [Citation Graph (, )][DBLP]
   
   
7. 
   FPGA-Based Architecture for Computing Testors. [Citation Graph (, )][DBLP]
   
   
8. 
   A Versatile Linear Insertion Sorter Based on a FIFO Scheme. [Citation Graph (, )][DBLP]
   
   
9. 
   FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. [Citation Graph (, )][DBLP]
   
   
10. 
    A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. [Citation Graph (, )][DBLP]
    
    
11. 
    FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. [Citation Graph (, )][DBLP]
    
    
12. 
    Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. [Citation Graph (, )][DBLP]