The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Claudia Feregrino: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino
    On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification. [Citation Graph (0, 0)][DBLP]
    CIARP, 2006, pp:665-673 [Conf]
  2. Jose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman
    The X-MatchLITE FPGA-Based Data Compressor. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1126-1132 [Conf]
  3. Jose Luis Nunez, Claudia Feregrino, Stephen Bateman, Simon Jones
    The X-MatchLITE FPGA-Based Data Compressor. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:255- [Conf]
  4. Jose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman
    X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:613-617 [Conf]
  5. Riad Stefo, Jose Luis Nunez, Claudia Feregrino, Sudipta Mahapatra, Simon Jones
    FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:643-647 [Conf]

Search in 0.016secs, Finished in 0.016secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002