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## Search the dblp DataBase
Zili Shao:
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## Publications of Author- Meilin Liu, Zili Shao, Chun Xue, Kevin F. Chen, Edwin Hsing-Mean Sha
**Multi-level Loop Fusion with Minimal Code Size.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2005, pp:348-0 [Conf] - Meilin Liu, Qingfeng Zhuge, Zili Shao, Kevin F. Chen, Edwin Hsing-Mean Sha
**Loop Fusion via Retiming for DSP Applications.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2004, pp:403-408 [Conf] - Bin Xiao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**Design and Analysis of Improved Shortest Path Tree Update for Network Routing.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2003, pp:82-87 [Conf] - Zili Shao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean Sha
**Defending Embedded Systems Against Buffer Overflow via Hardware/Software.**[Citation Graph (0, 0)][DBLP] ACSAC, 2003, pp:352-363 [Conf] - Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
**Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.**[Citation Graph (0, 0)][DBLP] ASAP, 2006, pp:178-181 [Conf] - Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha
**Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.**[Citation Graph (0, 0)][DBLP] ASAP, 2004, pp:224-234 [Conf] - Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha
**High-level synthesis for DSP applications using heterogeneous functional units.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:302-304 [Conf] - Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**General loop fusion technique for nested loops considering timing and code size.**[Citation Graph (0, 0)][DBLP] CASES, 2004, pp:190-201 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
**Iterational retiming: maximize iteration-level parallelism for nested loops.**[Citation Graph (0, 0)][DBLP] CODES+ISSS, 2005, pp:309-314 [Conf] - Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-Mean Sha
**Design space minimization with timing and code size optimization for embedded DSP.**[Citation Graph (0, 0)][DBLP] CODES+ISSS, 2003, pp:144-149 [Conf] - Mei Kang Qiu, Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha
**Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.**[Citation Graph (0, 0)][DBLP] EUC, 2006, pp:25-34 [Conf] - Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:121-130 [Conf] - Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha, Bin Xiao
**Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.**[Citation Graph (0, 0)][DBLP] EUC, 2004, pp:53-63 [Conf] - Bin Xiao, Jiadi Yu, Zili Shao, Minglu Li
**Distributed Proximity-Aware Peer Clustering in BitTorrent-Like Peer-to-Peer Networks.**[Citation Graph (0, 0)][DBLP] EUC, 2006, pp:375-384 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Optimizing Nested Loops with Iterational and Instructional Retiming.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:164-173 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Striping: Maximize Parallelism for Nested Loops.**[Citation Graph (0, 0)][DBLP] EUC, 2006, pp:405-414 [Conf] - Chun Xue, Zili Shao, Edwin Hsing-Mean Sha, Bin Xiao
**Optimizing Address Assignment for Scheduling Embedded DSPs.**[Citation Graph (0, 0)][DBLP] EUC, 2004, pp:64-73 [Conf] - Ying Chen, Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha
**Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems.**[Citation Graph (0, 0)][DBLP] ICPADS (2), 2005, pp:2-6 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.**[Citation Graph (0, 0)][DBLP] ICPADS (1), 2006, pp:375-382 [Conf] - Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications.**[Citation Graph (0, 0)][DBLP] ICPP, 2002, pp:613-620 [Conf] - Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**Timing Optimization of Nested Loops Considering Code Size for DSP Applications.**[Citation Graph (0, 0)][DBLP] ICPP, 2004, pp:475-482 [Conf] - Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha
**Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.**[Citation Graph (0, 0)][DBLP] IPDPS, 2004, pp:- [Conf] - Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai
**Loop scheduling for minimizing schedule length and switching activities.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:109-112 [Conf] - Bin Xiao, Jiannong Cao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
**Dynamic Update of Shortest Path Tree in OSPF.**[Citation Graph (0, 0)][DBLP] ISPAN, 2004, pp:18-23 [Conf] - Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge
**Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.**[Citation Graph (0, 0)][DBLP] ISSS, 2002, pp:144-149 [Conf] - Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao
**Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks.**[Citation Graph (0, 0)][DBLP] ITCC (1), 2004, pp:409-413 [Conf] - Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao
**Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software.**[Citation Graph (0, 0)][DBLP] ITCC (1), 2005, pp:780-785 [Conf] - Mei Kang Qiu, Meilin Liu, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Zili Shao
**Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.**[Citation Graph (0, 0)][DBLP] IASTED PDCS, 2005, pp:295-300 [Conf] - Zili Shao, Jiannong Cao, Keith C. C. Chan, Chun Xue, Edwin Hsing-Mean Sha
**Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks.**[Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 2006, v:66, n:9, pp:1129-1136 [Journal] - Zili Shao, Chun Xue, Qingfeng Zhuge, Mei Kang Qiu, Bin Xiao, Edwin Hsing-Mean Sha
**Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2006, v:55, n:4, pp:443-453 [Journal] - Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha
**Loop scheduling with timing and switching-activity minimization for VLIW DSP.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:165-185 [Journal] - Zili Shao, Qingfeng Zhuge, Chun Xue, Edwin Hsing-Mean Sha
**Efficient Assignment and Scheduling for Heterogeneous DSP Systems.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:6, pp:516-525 [Journal] - Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha
**Design optimization and space minimization considering timing and code size via retiming and unfolding.**[Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2006, v:30, n:4, pp:173-183 [Journal] - Meikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1641-1646 [Conf] - Meng Wang, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha
**Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.**[Citation Graph (0, 0)][DBLP] RTCSA, 2007, pp:12-19 [Conf] - Bin Xiao, Jiannong Cao, Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha
**Analysis and algorithms design for the partition of large-scale adaptive mobile wireless networks.**[Citation Graph (0, 0)][DBLP] Computer Communications, 2007, v:30, n:8, pp:1899-1912 [Journal] - Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2007, v:46, n:1, pp:55-73 [Journal] - Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2007, v:47, n:2, pp:153-167 [Journal] **Optimal loop parallelization for maximizing iteration-level parallelism.**[Citation Graph (, )][DBLP]**Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints.**[Citation Graph (, )][DBLP]**Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip.**[Citation Graph (, )][DBLP]**Interconnection Synthesis of MPSoC Architecture for Gamma Cameras.**[Citation Graph (, )][DBLP]**Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System.**[Citation Graph (, )][DBLP]**Parallel Network Intrusion Detection on Reconfigurable Platforms.**[Citation Graph (, )][DBLP]**A Loop-Based Key Management Scheme for Wireless Sensor Networks.**[Citation Graph (, )][DBLP]**A State-Based Predictive Approach for Leakage Reduction of Functional Units.**[Citation Graph (, )][DBLP]**Towards Successive Privacy Protection in Sensor Networks.**[Citation Graph (, )][DBLP]**A Formal Specification and Verification Framework for Designing and Verifying Reliable and Dependable Software for Computerized Numerical Control (CNC) Systems.**[Citation Graph (, )][DBLP]**Joint Sleep Scheduling and Mode Assignment in Wireless Cyber-Physical Systems.**[Citation Graph (, )][DBLP]**Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors.**[Citation Graph (, )][DBLP]**Topology-Aware Energy Efficient Task Assignment for Collaborative In-Network Processing in Distributed Sensor Systems.**[Citation Graph (, )][DBLP]**Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.**[Citation Graph (, )][DBLP]**RNFTL: a reuse-aware NAND flash translation layer for flash memory.**[Citation Graph (, )][DBLP]**Optimal Task Scheduling by Removing Inter-Core Communication Overhead for Streaming Applications on MPSoC.**[Citation Graph (, )][DBLP]**Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems.**[Citation Graph (, )][DBLP]**Topology Aware Task Allocation and Scheduling for Real-Time Data Fusion Applications in Networked Embedded Sensor Systems.**[Citation Graph (, )][DBLP]**Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts.**[Citation Graph (, )][DBLP]**MPSOC Architectural Design and Synthesis for Real-Time Biomedical Signal Processing in Gamma Cameras.**[Citation Graph (, )][DBLP]**Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems.**[Citation Graph (, )][DBLP]**ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems.**[Citation Graph (, )][DBLP]**Loop scheduling with memory access reduction under register constraints for DSP applications.**[Citation Graph (, )][DBLP]**Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.**[Citation Graph (, )][DBLP]
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