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## Search the dblp DataBase
Chun Xue:
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## Publications of Author- Meilin Liu, Zili Shao, Chun Xue, Kevin F. Chen, Edwin Hsing-Mean Sha
**Multi-level Loop Fusion with Minimal Code Size.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2005, pp:348-0 [Conf] - Meilin Liu, Chun Xue, Edwin Hsing-Mean Sha
**Optimizing Timing and Code Size Using Maximum Direct Loop Fusion.**[Citation Graph (0, 0)][DBLP] ISCA PDCS, 2006, pp:38-43 [Conf] - Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
**Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.**[Citation Graph (0, 0)][DBLP] ASAP, 2006, pp:178-181 [Conf] - Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha
**High-level synthesis for DSP applications using heterogeneous functional units.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:302-304 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha
**Iterational retiming: maximize iteration-level parallelism for nested loops.**[Citation Graph (0, 0)][DBLP] CODES+ISSS, 2005, pp:309-314 [Conf] - Mei Kang Qiu, Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha
**Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.**[Citation Graph (0, 0)][DBLP] EUC, 2006, pp:25-34 [Conf] - Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:121-130 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Optimizing Nested Loops with Iterational and Instructional Retiming.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:164-173 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Striping: Maximize Parallelism for Nested Loops.**[Citation Graph (0, 0)][DBLP] EUC, 2006, pp:405-414 [Conf] - Chun Xue, Zili Shao, Edwin Hsing-Mean Sha, Bin Xiao
**Optimizing Address Assignment for Scheduling Embedded DSPs.**[Citation Graph (0, 0)][DBLP] EUC, 2004, pp:64-73 [Conf] - Ying Chen, Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha
**Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems.**[Citation Graph (0, 0)][DBLP] ICPADS (2), 2005, pp:2-6 [Conf] - Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha
**Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.**[Citation Graph (0, 0)][DBLP] ICPADS (1), 2006, pp:375-382 [Conf] - Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha
**Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.**[Citation Graph (0, 0)][DBLP] IPDPS, 2004, pp:- [Conf] - Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao
**Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks.**[Citation Graph (0, 0)][DBLP] ITCC (1), 2004, pp:409-413 [Conf] - Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao
**Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software.**[Citation Graph (0, 0)][DBLP] ITCC (1), 2005, pp:780-785 [Conf] - Mei Kang Qiu, Meilin Liu, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Zili Shao
**Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.**[Citation Graph (0, 0)][DBLP] IASTED PDCS, 2005, pp:295-300 [Conf] - Zili Shao, Jiannong Cao, Keith C. C. Chan, Chun Xue, Edwin Hsing-Mean Sha
**Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks.**[Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 2006, v:66, n:9, pp:1129-1136 [Journal] - Zili Shao, Chun Xue, Qingfeng Zhuge, Mei Kang Qiu, Bin Xiao, Edwin Hsing-Mean Sha
**Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2006, v:55, n:4, pp:443-453 [Journal] - Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha
**Loop scheduling with timing and switching-activity minimization for VLIW DSP.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:165-185 [Journal] - Zili Shao, Qingfeng Zhuge, Chun Xue, Edwin Hsing-Mean Sha
**Efficient Assignment and Scheduling for Heterogeneous DSP Systems.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:6, pp:516-525 [Journal] - Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha
**Design optimization and space minimization considering timing and code size via retiming and unfolding.**[Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2006, v:30, n:4, pp:173-183 [Journal] - Meikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1641-1646 [Conf] - Meng Wang, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha
**Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.**[Citation Graph (0, 0)][DBLP] RTCSA, 2007, pp:12-19 [Conf] - Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2007, v:46, n:1, pp:55-73 [Journal] - Chun Xue, Zili Shao, Edwin Hsing-Mean Sha
**Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2007, v:47, n:2, pp:153-167 [Journal] **Loop Fusion Technique with Minimal Memory Cost via Retiming.**[Citation Graph (, )][DBLP]**Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System.**[Citation Graph (, )][DBLP]**Parallel Network Intrusion Detection on Reconfigurable Platforms.**[Citation Graph (, )][DBLP]**Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.**[Citation Graph (, )][DBLP]
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