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Hiroki Matsutani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2006, pp:24-31 [Conf]
  2. Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano
    A Parametric Study of Scalable Interconnects on FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:130-135 [Conf]
  3. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima
    An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:163-170 [Conf]
  4. Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai
    Mobile Gateways for Mobile Ad-Hoc Networks with Network Mobility Support. [Citation Graph (0, 0)][DBLP]
    ICN (2), 2005, pp:361-368 [Conf]
  5. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
    Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2005, pp:273-280 [Conf]
  6. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. [Citation Graph (0, 0)][DBLP]
    ISPA, 2006, pp:207-218 [Conf]
  7. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:1343-1349 [Conf]
  8. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:75- [Conf]
  9. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]

  10. Run-time power gating of on-chip routers using look-ahead routing. [Citation Graph (, )][DBLP]


  11. A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. [Citation Graph (, )][DBLP]


  12. A link removal methodology for Networks-on-Chip on reconfigurable systems. [Citation Graph (, )][DBLP]


  13. MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. [Citation Graph (, )][DBLP]


  14. Prediction router: Yet another low latency on-chip router architecture. [Citation Graph (, )][DBLP]


  15. Balanced Dimension-Order Routing for k-ary n-cubes. [Citation Graph (, )][DBLP]


  16. Evaluation of a multicore reconfigurable architecture with variable core sizes. [Citation Graph (, )][DBLP]


  17. An on/off link activation method for low-power ethernet in PC clusters. [Citation Graph (, )][DBLP]


  18. Three-Dimensional Layout of On-Chip Tree-Based Networks. [Citation Graph (, )][DBLP]


  19. An On/Off Link Activation Method for Power Regulation in InfiniBand. [Citation Graph (, )][DBLP]


  20. A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. [Citation Graph (, )][DBLP]


  21. Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. [Citation Graph (, )][DBLP]


  22. Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. [Citation Graph (, )][DBLP]


  23. Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. [Citation Graph (, )][DBLP]


  24. A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. [Citation Graph (, )][DBLP]


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