The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Hideharu Amano: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2006, pp:24-31 [Conf]
  2. Masato Sumiyoshi, Takashi Midorikawa, Yasuki Tanabe, Hideharu Amano
    Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2004, pp:296-301 [Conf]
  3. Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano
    A Routing Algorithm for DS-WDM Ring. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:562-565 [Conf]
  4. Takahiro Kawaguchi, Takashi Fujiwara, Katsuto Sakamoto, Keisuke Iwai, Hideharu Amano
    Floating Point Arithmetic Unit for the Custom Processor Maple. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:578-580 [Conf]
  5. Tomohiro Otsuka, Konosuke Watanabe, Junichiro Tsuchiya, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Hideharu Amano
    Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 2003, pp:738-743 [Conf]
  6. Masaki Wakabayashi, Keisuke Inoue, Hideharu Amano
    ISIS: Multiprocessor Simulator Library. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:198-200 [Conf]
  7. Katsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, Hideharu Amano
    Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:12-18 [Conf]
  8. Hideharu Amano, Yuichiro Shibata
    Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:453-457 [Conf]
  9. Takahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano
    A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:31-32 [Conf]
  10. Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano
    A prototype chip of multicontext FPGA with DRAM for virtual hardware. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:17-18 [Conf]
  11. Masahiko Kawamura, Hideharu Amano
    Future reconfigurable computing system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:798- [Conf]
  12. Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano
    The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:337-338 [Conf]
  13. Yasunori Osana, Tomonori Fukushima, Hideharu Amano
    ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:731-733 [Conf]
  14. Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
    The impact of output selection function on adaptive routing. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2001, pp:241-246 [Conf]
  15. Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh
    Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems. [Citation Graph (0, 0)][DBLP]
    CCGRID, 2003, pp:318-325 [Conf]
  16. Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano
    Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2003, pp:395-0 [Conf]
  17. Chizuko Saito, Hideharu Amano, Tomohiro Kudoh, Hideo Aiso
    An Adaptable Cluster Structure of (SM)²-II. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1986, pp:53-60 [Conf]
  18. Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano
    A Parametric Study of Scalable Interconnects on FPGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:130-135 [Conf]
  19. Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura
    Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. [Citation Graph (0, 0)][DBLP]
    EUC, 2004, pp:301-311 [Conf]
  20. Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano
    Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:793-797 [Conf]
  21. Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki
    Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:315-316 [Conf]
  22. Yuichiro Shibata, Masaki Uno, Hideharu Amano, K. Furuta, Taro Fujii, Masato Motomura
    A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:295-296 [Conf]
  23. Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano
    A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:291-294 [Conf]
  24. Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
    Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:328-329 [Conf]
  25. Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano
    Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:265- [Conf]
  26. Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa
    An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:347-352 [Conf]
  27. Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki
    Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:464-473 [Conf]
  28. Hideharu Amano, Akiya Jouraku, Kenichiro Anjo
    A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:161-170 [Conf]
  29. Hideharu Amano, Yuichiro Shibata, Masaki Uno
    Reconfigurable Systems: New Activities in Asia. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:585-594 [Conf]
  30. Xiao-yu Chen, Xiao-ping Ling, Hideharu Amano
    Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:208-219 [Conf]
  31. Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano
    ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:200-209 [Conf]
  32. Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri
    Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:666-669 [Conf]
  33. Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano
    RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1118-1121 [Conf]
  34. Naoto Kaneko, Hideharu Amano
    A General Hardware Design Model for Multicontext FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1037-1047 [Conf]
  35. Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo
    Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:171-180 [Conf]
  36. Kazumasa Nukata, Yuichiro Shibata, Hideharu Amano, Yuichiro Anzai
    A reconfigurable sensor-data processing system for personal robots. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:491-500 [Conf]
  37. Yasunori Osana, Tomonori Fukushima, Hideharu Amano
    Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:766-775 [Conf]
  38. Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
    A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:574-577 [Conf]
  39. Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano
    An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:55-64 [Conf]
  40. Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano
    Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:685-694 [Conf]
  41. Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano
    A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:475-484 [Conf]
  42. Masato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano
    Stochastic Simulation for Biochemical Reactions on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:105-114 [Conf]
  43. Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
    The Design of Scalable Stochastic Biochemical Simulator on FPGA. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:339-340 [Conf]
  44. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima
    An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:163-170 [Conf]
  45. Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano
    RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:129-136 [Conf]
  46. Hiroaki Nishi, Koji Tasho, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
    A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing. [Citation Graph (0, 0)][DBLP]
    HPDC, 2000, pp:296-297 [Conf]
  47. Hideharu Amano
    A Fault Tolerant Batcher Network. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:441-444 [Conf]
  48. Hideharu Amano, Kalidou Gaye
    A Batcher Double Omega Network with Combining. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:718-719 [Conf]
  49. Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa
    Multistage Interconnection Networks with Multiple Outlets. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:1-8 [Conf]
  50. Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano
    L-Turn Routing: An Adaptive Routing in Irregular Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, 2001, pp:383-392 [Conf]
  51. Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano
    Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. [Citation Graph (0, 0)][DBLP]
    ICPP, 2003, pp:527-0 [Conf]
  52. Tomohiro Kudoh, Hideharu Amano, Takashi Matsumoto, Kei Hiraki, Yulu Yang, Katsunobu Nishimura, Koichi Yoshimura, Yasuhito Fukushima
    Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1995, pp:186-193 [Conf]
  53. Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa
    A Parallel Logic Simulation Algorithm Based on Query. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1992, pp:262-266 [Conf]
  54. Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
    VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:567-576 [Conf]
  55. Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano
    Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. [Citation Graph (0, 0)][DBLP]
    ICPP, 2006, pp:479-486 [Conf]
  56. Masashi Sasahara, Jun Terada, Luo Zhou, Kalidou Gaye, Jun-ichi Yamato, Satoshi Ogura, Hideharu Amano
    SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:117-120 [Conf]
  57. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
    Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2005, pp:273-280 [Conf]
  58. Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano
    Internal Parallelization of Data-Driven Virtual Hardware. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 1999, pp:366-0 [Conf]
  59. Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hidenori Miyazaki, Koichi Higure, Xiao-ping Ling, Hideharu Amano
    Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 1999, pp:346-351 [Conf]
  60. Hideharu Amano, Takuya Terasawa, Tomohiro Kudoh
    Cache with Synchronization Mechanism. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:1001-1006 [Conf]
  61. Hideharu Amano, Luo Zhou, Kalidou Gaye
    SSS (Simple Serial Synchronized)-MIN: A Novel Multi Stage Interconnection Architecture for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1992, pp:571-577 [Conf]
  62. Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
    BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  63. Yasunori Osana, Tomonori Fukushima, Masato Yoshimi, Yow Iwaoka, Yuichiro Shibata, Hiroaki Kitano, Akira Funahashi, Noriko Hiroi, Hideharu Amano
    An FPGA-Based, Multi-model Simulation Method for Biochemical Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  64. Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Ling, Hideharu Amano
    HOSMII: A Virtual Hardware Integrated with DRAM. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:85-90 [Conf]
  65. Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano
    A cost-effective context memory structure for dynamically reconfigurable processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  66. Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, T. Nakamura, T. Nishimura, Hideharu Amano
    Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  67. Taisuke Boku, Shigehiro Nomura, Hideharu Amano
    IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:365-372 [Conf]
  68. Hideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso
    (SM)²-II: A New Version of the Sparse Matrix Solving Machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:100-107 [Conf]
  69. Hideharu Amano, Takaichi Yoshida, Hideo Aiso
    (SM)2: Sparse Matrix Solving Machine [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:213-220 [Conf]
  70. Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh
    Adaptive Routing on the Recursive Diagonal Torus. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1997, pp:171-182 [Conf]
  71. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. [Citation Graph (0, 0)][DBLP]
    ISPA, 2006, pp:207-218 [Conf]
  72. Qin Fan, Yulu Yang, Akira Funahashi, Hideharu Amano
    A Torus Assignment for an Interconnection Network Recursive Diagonal Torus. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1999, pp:74-79 [Conf]
  73. Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano
    Wavelength Division Multiple Access Ring - Virtual Topology on a Simple Ring Network. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1997, pp:30-36 [Conf]
  74. Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi
    Routing Algorithms Based on 2D Turn Model for Irregular Networks. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2002, pp:289-294 [Conf]
  75. Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
    On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2000, pp:186-194 [Conf]
  76. Jun Miyazaki, Hideharu Amano, Kenji Takeda, Hideo Aiso
    A Shared Memory Architecture for MANJI Production System Machine. [Citation Graph (0, 0)][DBLP]
    IWDM, 1987, pp:517-531 [Conf]
  77. Jun Miyazaki, Kenji Takeda, Hideharu Amano, Hideo Aiso
    A New Version of a Parallel Production System Machine, MANJI-II. [Citation Graph (0, 0)][DBLP]
    IWDM, 1989, pp:317-330 [Conf]
  78. Fumiharu Morisawa, Daisuke Kawakami, Kensuke Tanaka, Hideharu Amano
    An Educational System of LSI Design with Free-Wares for VDEC. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:61-62 [Conf]
  79. Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
    Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2002, pp:9-14 [Conf]
  80. Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano
    A New Memory Module for Memory Intensive Applications. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:123-128 [Conf]
  81. Xiao-ping Ling, Hideharu Amano
    A static scheduling system for a parallel machine (SM)2-II. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1989, pp:118-135 [Conf]
  82. Xiao-ping Ling, Hideharu Amano
    Performance evaluation of WASMII: a data driven computer on a virtual hardware. [Citation Graph (0, 0)][DBLP]
    PARLE, 1993, pp:610-621 [Conf]
  83. Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo
    Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. [Citation Graph (0, 0)][DBLP]
    PDCAT, 2005, pp:778-780 [Conf]
  84. Junji Yamamoto, D. Hattori, Jun-ichi Yamato, T. Tokuyoshi, Y. Yamaguchi, Hideharu Amano
    A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:68-71 [Conf]
  85. Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
    A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:461-467 [Conf]
  86. Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano
    Implementation of ISIS-SimpleScalar. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:117-123 [Conf]
  87. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
    The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1431-1437 [Conf]
  88. Xiao-ping Ling, Yuichiro Shibata, Hidenori Miyazaki, Hideharu Amano, Koichi Higure
    Total System Image of the Reconfigurable Machine WASMII. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1997, pp:1092-1096 [Conf]
  89. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:1343-1349 [Conf]
  90. Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano
    Coherence Protocol for Home Proxy Cache on RHiNET. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  91. Noriaki Suzuki, Hideharu Amano
    Performance Evaluation of Instruction Set Architecture of MBP-Light: A Distributed Memory Controller for a Large Scale Multiprocessor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:1155-1164 [Conf]
  92. Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano
    Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:1148-1154 [Conf]
  93. Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi
    Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:591-595 [Conf]
  94. Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
    Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2002, v:5, n:1, pp:7-17 [Journal]
  95. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
    MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. [Citation Graph (0, 0)][DBLP]
    IEICE Transactions, 2005, v:88, n:1, pp:109-118 [Journal]
  96. Kyotaro Suzuki, Hideharu Amano, Yoshiyasu Takefuji
    Neural network parallel computing for multi-layer channel routing problems. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1995, v:8, n:2, pp:141-156 [Journal]
  97. S. Nishimura, K. Harasawa, N. Matsudaira, S. Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano
    RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection. [Citation Graph (0, 0)][DBLP]
    New Generation Comput., 2000, v:18, n:2, pp:187-0 [Journal]
  98. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
    Path selection algorithm: the strategy for designing deterministic routing from alternative paths. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2005, v:31, n:1, pp:117-130 [Journal]
  99. Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano
    The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2005, v:31, n:3-4, pp:352-370 [Journal]
  100. Takuya Terasawa, Ou Yamamoto, Tomohiro Kudoh, Hideharu Amano
    A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1995, v:21, n:5, pp:701-730 [Journal]
  101. Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano
    Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:9, pp:1081-1103 [Journal]
  102. Hiroaki Nishi, Koji Tasho, Tomohiro Kudoh, Hideharu Amano
    A network switch for supporting high-performance parallel processing by computers distributed in local areas. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:14, pp:24-33 [Journal]
  103. Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano
    A study on snoop cache systems for single-chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:2, pp:62-72 [Journal]
  104. Ou Yamamoto, Takuya Terasawa, Hideharu Amano
    An analysis of fairness and overhead in the arbitration protocol of the IEEE Futurebus standard. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:13, pp:66-77 [Journal]
  105. Hideharu Amano, Taisuke Boku, Tomohiro Kudoh
    (SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:7, pp:889-905 [Journal]
  106. Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
    A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:12, pp:1425-1437 [Journal]
  107. Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano
    Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:8, pp:747-759 [Journal]
  108. Yulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, Toshinori Sueyoshi
    Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:7, pp:701-715 [Journal]
  109. Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano
    An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:3, pp:320-333 [Journal]
  110. Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano
    MMLRU Selection Function: An Output Selection Function on Adaptive Routing. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:1-6 [Conf]
  111. Hideharu Amano, Yohei Hasegawa, Shohei Abe, K. Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, T. Nakamura, T. Nishimura
    A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  112. Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
    An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  113. Yasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
    Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  114. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:75- [Conf]
  115. Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano
    Performance Improvement Methodology for ClearSpeed's CSX600. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:77- [Conf]
  116. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
    Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]
  117. Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
    Performance evaluation on low-latency communication mechanism of DIMMnet-2. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2007, pp:57-62 [Conf]
  118. Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano
    Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:115-121 [Conf]
  119. Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano
    Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:9, pp:1282-1295 [Journal]

  120. Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA. [Citation Graph (, )][DBLP]


  121. Cache Controller Design on Ultra Low Leakage Embedded Processors. [Citation Graph (, )][DBLP]


  122. Run-time power gating of on-chip routers using look-ahead routing. [Citation Graph (, )][DBLP]


  123. MEMOnet : Network interface plugged into a memory slot. [Citation Graph (, )][DBLP]


  124. A Method for Capturing State Data on Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]


  125. Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. [Citation Graph (, )][DBLP]


  126. Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. [Citation Graph (, )][DBLP]


  127. Japanese Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]


  128. Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]


  129. A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. [Citation Graph (, )][DBLP]


  130. Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. [Citation Graph (, )][DBLP]


  131. A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. [Citation Graph (, )][DBLP]


  132. A High Speed License Plate Recognition System on an FPGA. [Citation Graph (, )][DBLP]


  133. FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method. [Citation Graph (, )][DBLP]


  134. A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. [Citation Graph (, )][DBLP]


  135. Practical implementation of a network-based stochastic biochemical simulation system on an FPGA. [Citation Graph (, )][DBLP]


  136. A link removal methodology for Networks-on-Chip on reconfigurable systems. [Citation Graph (, )][DBLP]


  137. Power reduction techniques for Dynamically Reconfigurable Processor Arrays. [Citation Graph (, )][DBLP]


  138. Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]


  139. MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. [Citation Graph (, )][DBLP]


  140. Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]


  141. Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs. [Citation Graph (, )][DBLP]


  142. Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator. [Citation Graph (, )][DBLP]


  143. Prediction router: Yet another low latency on-chip router architecture. [Citation Graph (, )][DBLP]


  144. A fine-grain dynamic sleep control scheme in MIPS R3000. [Citation Graph (, )][DBLP]


  145. Balanced Dimension-Order Routing for k-ary n-cubes. [Citation Graph (, )][DBLP]


  146. Evaluation of a multicore reconfigurable architecture with variable core sizes. [Citation Graph (, )][DBLP]


  147. An on/off link activation method for low-power ethernet in PC clusters. [Citation Graph (, )][DBLP]


  148. Three-Dimensional Layout of On-Chip Tree-Based Networks. [Citation Graph (, )][DBLP]


  149. Adaptive power gating for function units in a microprocessor. [Citation Graph (, )][DBLP]


  150. Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. [Citation Graph (, )][DBLP]


  151. An On/Off Link Activation Method for Power Regulation in InfiniBand. [Citation Graph (, )][DBLP]


  152. Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. [Citation Graph (, )][DBLP]


  153. A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. [Citation Graph (, )][DBLP]


  154. Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator. [Citation Graph (, )][DBLP]


  155. A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster. [Citation Graph (, )][DBLP]


  156. A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. [Citation Graph (, )][DBLP]


  157. Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. [Citation Graph (, )][DBLP]


  158. Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. [Citation Graph (, )][DBLP]


  159. Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. [Citation Graph (, )][DBLP]


  160. A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. [Citation Graph (, )][DBLP]


  161. A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA. [Citation Graph (, )][DBLP]


  162. Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor. [Citation Graph (, )][DBLP]


  163. Design and implementation of reconfigurable sensing system for networked robots. [Citation Graph (, )][DBLP]


Search in 3.109secs, Finished in 3.115secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002