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Nohpill Park: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. N.-J. Park, Byoungjae Jin, K. M. George, Nohpill Park
    Performance Modeling and Analysis of Distributed Web Server (DWS) System with Access Frequency Distribution (AFD). [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2003, pp:224-229 [Conf]
  2. Wirachai Yanphanich, K. M. George, Nohpill Park
    Multi-node Failure Detection and Recovery in a Pipeline Cluster. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2003, pp:244-249 [Conf]
  3. B. D. Gaston, K. M. George, Nohpill Park
    An Approach to Protection Using a Non-Persistent Client-Side Page Proxy. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2005, pp:226-231 [Conf]
  4. T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
    Fault tolerant clockless wave pipeline design. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:350-356 [Conf]
  5. Y. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi
    Repairability Evaluation of Embedded Multiple Region DRAMs. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:428-436 [Conf]
  6. D. G. Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi
    Testing of programmable logic devices (PLD) with faulty resources. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:76-84 [Conf]
  7. Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi
    Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:161-169 [Conf]
  8. Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
    Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:419-427 [Conf]
  9. T. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer
    Reliability Modeling and Assurance of Clockless Wave Pipeline. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:442-450 [Conf]
  10. T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri
    Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:34-0 [Conf]
  11. Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park
    A Test-Vector Generation Methodology for Crosstalk Noise Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:40-50 [Conf]
  12. Fabrizio Lombardi, Nohpill Park
    Testing Layered Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:293-304 [Conf]
  13. N.-J. Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi
    Regressive Testing for System-on-Chip with Unknown-Good-Yield. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:393-400 [Conf]
  14. Nohpill Park, Fabrizio Lombardi
    Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:192-200 [Conf]
  15. Nohpill Park, Fred J. Meyer, Fabrizio Lombardi
    Quality-Effective Repair of Multichip Module Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:47-55 [Conf]
  16. Nohpill Park, S. J. Ruiwale, Fabrizio Lombardi
    Testing the Configurability of Dynamic FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:311-319 [Conf]
  17. Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer
    QCA-Based Majority Gate Design under Radius of Effect-Induced Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:217-228 [Conf]
  18. Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park
    Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:80-88 [Conf]
  19. Shanrui Zhang, Minsu Choi, Nohpill Park
    Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:356-364 [Conf]
  20. Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi
    Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:48-56 [Conf]
  21. Yinan N. Shen, Nohpill Park, Fabrizio Lombardi
    Space Cutting Approaches for Repairing Memories. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:106-111 [Conf]
  22. X. Tan, J. Tong, P. Tan, Nohpill Park, Fabrizio Lombardi
    An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:608-613 [Conf]
  23. José Salinas, Nohpill Park, U. Arunkumar, Fabrizio Lombardi
    Conformance Testing of Time-Dependent Protocols. [Citation Graph (0, 0)][DBLP]
    ICECCS, 1996, pp:257-264 [Conf]
  24. Minsu Choi, Nohpill Park, Fabrizio Lombardi
    Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  25. B. Jang, Nohpill Park, K. M. George, G. E. Hedrick
    Modeling and Evaluation of the Interconnection-driven Repairability for Distributed Embedded Memory Cores on Chip. [Citation Graph (0, 0)][DBLP]
    Modelling, Identification and Control, 2003, pp:403-408 [Conf]
  26. Minsu Choi, Nohpill Park
    Teaching Nanotechnology by Introducing Crossbar-Based Architecture and Quantum-Dot Cellular Automata. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:29-30 [Conf]
  27. Minsu Choi, Hardy J. Pottinger, Nohpill Park, Yong-Bin Kim
    Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:121-122 [Conf]
  28. J. Y. Shin, N.-J. Park, Nohpill Park, K. M. George
    Exploratory Data Analysis with Bivariate Dependence Functions. [Citation Graph (0, 0)][DBLP]
    MSV, 2006, pp:217-223 [Conf]
  29. Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
    Optimal Spare Utilization in Repairable and Reliable Memory Cores. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:64-71 [Conf]
  30. Mohammad A. Al-Hashimi, Huay-min H. Pu, Nohpill Park, Fabrizio Lombardi
    Dependability under Malicious Agreement in N-modular Redundancy-on-Demand Systems. [Citation Graph (0, 0)][DBLP]
    NCA, 2001, pp:80-93 [Conf]
  31. Minsu Choi, N.-J. Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
    Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. [Citation Graph (0, 0)][DBLP]
    NCA, 2003, pp:341-0 [Conf]
  32. Wirachai Yanphanich, K. M. George, Nohpill Park
    A Fault Tolerant Pipelined Cluster Model. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:508-514 [Conf]
  33. T. Feng, Nohpill Park, K. M. George
    Hardware/Software Co-Reliability of Field Reconfigurable Multi-Processor-Memory Systems with Redundant Bus. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:1886-1890 [Conf]
  34. Wirachai Yanphanich, K. M. George, Nohpill Park
    Clustering with Mobile Agents. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:429-435 [Conf]
  35. Fabrizio Lombardi, Nohpill Park, Mohammad A. Al-Hashimi, Huay-min H. Pu
    Modeling the Dependability of N-Modular Redundancy on Demand under Malicious Agreement. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:68-75 [Conf]
  36. Minsu Choi, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
    Hardware/Software Co-Reliability of Configurable Digital Systems. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:67-74 [Conf]
  37. Minsu Choi, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi
    Connectivity-Based Multichip Module Repair. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:19-26 [Conf]
  38. Srivastav Sethupathy, Nohpill Park, Marcin Paprzycki
    Logic Restructuring for Delay Balancing in Wave-Pipelined Circuits: An Integer Programming Approach. [Citation Graph (0, 0)][DBLP]
    SYNASC, 2005, pp:182-188 [Conf]
  39. Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi
    Design Verification of FPGA Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:2, pp:66-73 [Journal]
  40. Minsu Choi, Nohpill Park, Vincenzo Piuri, Yong-Bin Kim, Fabrizio Lombardi
    Balanced dual-stage repair for dependable embedded memory cores. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:281-285 [Journal]
  41. Bin Liu, Fabrizio Lombardi, Nohpill Park, Minsu Choi
    Testing Layered Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:710-722 [Journal]
  42. Fred J. Meyer, Nohpill Park
    Predicting Defect-Tolerant Yield in the Embedded Core Context. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1470-1479 [Journal]
  43. Myungsu Choi, Zachary D. Patitz, Byoungjae Jin, Feng Tao, Nohpill Park, Minsu Choi
    Designing layout-timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:9, pp:551-567 [Journal]
  44. Jun Zhao, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi
    Sequential diagnosis of processor array systems. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2004, v:53, n:4, pp:487-498 [Journal]
  45. Jun Zhao, Fred J. Meyer, Fabrizio Lombardi, Nohpill Park
    Maximal diagnosis of interconnects of random access memories. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:423-434 [Journal]
  46. Farzin Karimi, V. Swamy Irrinki, T. Crosby, Nohpill Park, Fabrizio Lombardi
    Parallel testing of multi-port static random access memories. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:3-21 [Journal]

  47. Modeling and Evaluation of Threshold Defect Tolerance. [Citation Graph (, )][DBLP]


  48. An Extraction Method of Lip Movement Images from Successive Image Frames in the Speech Activity Extraction Process. [Citation Graph (, )][DBLP]


  49. A Probabilistic Risk Estimation with Multiple Regression Dependent Dummy Variable Method using Logit Transformation. [Citation Graph (, )][DBLP]


  50. Leakage Minimization Technique for Nanoscale CMOS VLSI. [Citation Graph (, )][DBLP]


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