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Ron Ho: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yun Zhang, Mihai Burcea, Victor Cheng, Ron Ho, Michael Voss
    An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2004, pp:256-263 [Conf]
  2. Ron Ho, Jonathan Gainsley, Robert J. Drost
    Long Wires and Asynchronous Control. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:240-249 [Conf]
  3. Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks
    On-chip samplers for test and debug of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:153-162 [Conf]
  4. Robert J. Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok V. Krishnamoorthy, Danny Cohen, John E. Cunningham, Bernard Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, Ivan E. Sutherland
    Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication. [Citation Graph (0, 0)][DBLP]
    Hot Interconnects, 2005, pp:13-22 [Conf]
  5. Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz
    Interconnect scaling implications for CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:425-429 [Conf]
  6. Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
    Smart Memories: a modular reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:161-171 [Conf]
  7. Ron Ho
    High-performance ULSI: the real limiter to interconnect scaling. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:3- [Conf]
  8. Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman
    Robust Energy-Efficient Adder Topologies. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:16-28 [Conf]
  9. John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh
    Research Challenges for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:96-108 [Journal]

  10. Optical Interconnects for Present and Future High-Performance Computing Systems. [Citation Graph (, )][DBLP]

  11. Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. [Citation Graph (, )][DBLP]

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