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Yu Hu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yong Zhao, Yu Hu
    GRESS - a Grid Replica Selection Service. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2003, pp:423-429 [Conf]
  2. Zhen-Hua Ling, Yu Hu, Ren-Hua Wang
    A Novel Source Analysis Method by Matching Spectral Characters of LF Model with STRAIGHT Spectrum. [Citation Graph (0, 0)][DBLP]
    ACII, 2005, pp:441-448 [Conf]
  3. Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan
    Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:198-203 [Conf]
  4. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
    DraXRouter: global routing in X-Architecture with dynamic resource assignment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:618-623 [Conf]
  5. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
    Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:53-58 [Conf]
  6. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xiaodong Hu, Guiying Yan
    An-OARSMan: obstacle-avoiding routing tree construction with good length performance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:7-12 [Conf]
  7. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Rapid and Energy-Efficient Testing for Embedded Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:8-13 [Conf]
  8. Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra
    Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:372-377 [Conf]
  9. Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
    Pair Balance-Based Test Scheduling for SOCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:236-241 [Conf]
  10. Yu Hu, Yan Lin, Lei He, Tim Tuan
    Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:478-483 [Conf]
  11. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:298-305 [Conf]
  12. Gary S. H. Tan, Yu Hu, Farshad Moradi
    Automatic SOM Compatibility Check and FOM Development. [Citation Graph (0, 0)][DBLP]
    DS-RT, 2003, pp:60-67 [Conf]
  13. Yu Hu, Qing Li, C. C. Jay Kuo
    Efficient implementation of elliptic curve cryptography (ECC) on VLIW-micro-architecture media processor. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:879-882 [Conf]
  14. Ren-Hua Wang, Qingfeng Liu, Yu Hu, Bo Yin, Xiaoru Wu
    KD2000 Chinese Text-To-Speech System. [Citation Graph (0, 0)][DBLP]
    ICMI, 2000, pp:300-307 [Conf]
  15. Yu Hu, Qiang Huo
    An HMM Compensation Approach Using Unscented Transformation for Noisy Speech Recognition. [Citation Graph (0, 0)][DBLP]
    ISCSLP, 2006, pp:346-357 [Conf]
  16. Yan Lin, Yu Hu, Lei He, Vijay Raghunat
    An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:168-173 [Conf]
  17. Zhe Feng 0002, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
    An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:48-55 [Conf]
  18. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
    Using MUXs Network to Hide Bunches of Scan Chains. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:238-243 [Conf]
  19. Yu Hu, Xiaowei Li, Huawei Li, Xiao-Qing Wen
    Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:175-182 [Conf]
  20. Yu Hu, Qing Li, C. C. Jay Kuo
    Run-Time Power Consumption Modeling for Embedded Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:353-356 [Conf]
  21. Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
    A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:344-353 [Conf]
  22. Yu Hu, Qing Li, Siwei Ma, C. C. Jay Kuo
    Fast H.264/AVC Inter-Mode Decision with RDC Optimization. [Citation Graph (0, 0)][DBLP]
    IIH-MSP, 2006, pp:511-516 [Conf]
  23. Yu Hu, Tong Jing, Zhe Feng 0002, Xianlong Hong, Xiaodong Hu, Guiying Yan
    ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:1, pp:147-152 [Journal]
  24. Yu Hu, Qing Li, Siwei Ma, C. C. Jay Kuo
    Decoder-Friendly Adaptive Deblocking Filter (DF-ADF) Mode Decision in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3976-3979 [Conf]
  25. Jie Don, Yu Hu, Yinhe Han, Xiaowei Li
    An on-chip combinational decompressor for reducing test data volume. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  26. Hao Yu, Yu Hu, Chunchen Liu, Lei He
    Minimal skew clock embedding considering time variant temperature gradient. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:173-180 [Conf]
  27. Yu Hu, King Ho Tam, Tong Jing, Lei He
    Fast dual-vdd buffering based on interconnect prediction and sampling. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:95-102 [Conf]
  28. Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang
    Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2007, v:22, n:5, pp:673-680 [Journal]
  29. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra
    Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:531-540 [Journal]

  30. A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. [Citation Graph (, )][DBLP]

  31. On reducing both shift and capture power for scan-based testing. [Citation Graph (, )][DBLP]

  32. Localized random access scan: Towards low area and routing overhead. [Citation Graph (, )][DBLP]

  33. DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. [Citation Graph (, )][DBLP]

  34. Robust test generation for power supply noise induced path delay faults. [Citation Graph (, )][DBLP]

  35. A Novel Example-Based Super-Resolution Approach Based on Patch Classification and the KPCA Prior Model. [Citation Graph (, )][DBLP]

  36. Face Recognition Using Modular Locality Preserving Projections. [Citation Graph (, )][DBLP]

  37. FPGA area reduction by multi-output function based sequential resynthesis. [Citation Graph (, )][DBLP]

  38. Rewiring for robustness. [Citation Graph (, )][DBLP]

  39. iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. [Citation Graph (, )][DBLP]

  40. Diagnosis of multiple arbitrary faults with mask and reinforcement effect. [Citation Graph (, )][DBLP]

  41. IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults. [Citation Graph (, )][DBLP]

  42. RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. [Citation Graph (, )][DBLP]

  43. Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. [Citation Graph (, )][DBLP]

  44. A Scan-Based Delay Test Method for Reduction of Overtesting. [Citation Graph (, )][DBLP]

  45. Adaptive Diagnostic Pattern Generation for Scan Chains. [Citation Graph (, )][DBLP]

  46. A Case Study on At-Speed Testing for a Gigahertz Microprocessor. [Citation Graph (, )][DBLP]

  47. Building a faster boolean matcher using bloom filter. [Citation Graph (, )][DBLP]

  48. Pricing of Online Advertising: Cost-Per-Click-Through Vs. Cost-Per-Action. [Citation Graph (, )][DBLP]

  49. Reliability Optimization of Reconfigurable Computing-Based Fault-Tolerant System. [Citation Graph (, )][DBLP]

  50. Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. [Citation Graph (, )][DBLP]

  51. Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. [Citation Graph (, )][DBLP]

  52. On capture power-aware test data compression for scan-based testing. [Citation Graph (, )][DBLP]

  53. IPR: In-Place Reconfiguration for FPGA fault tolerance. [Citation Graph (, )][DBLP]

  54. Robust FPGA resynthesis based on fault-tolerant Boolean matching. [Citation Graph (, )][DBLP]

  55. Face Recognition using 3D Summation Invariant Features. [Citation Graph (, )][DBLP]

  56. Joint Rate-Distortion-Complexity Optimization for H.264 Motion Search. [Citation Graph (, )][DBLP]

  57. Worst case timing jitter and amplitude noise in differential signaling. [Citation Graph (, )][DBLP]

  58. Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. [Citation Graph (, )][DBLP]

  59. Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures. [Citation Graph (, )][DBLP]

  60. Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. [Citation Graph (, )][DBLP]

  61. Heteroscedastic discriminant analysis with two-dimensional constraints. [Citation Graph (, )][DBLP]

  62. Minimum word classification error training of HMMS for automatic speech recognition. [Citation Graph (, )][DBLP]

  63. A trust region based optimization for maximum mutual information estimation of HMMS in speech recognition. [Citation Graph (, )][DBLP]

  64. An algorithm on discrimination of point-set in polyhedron based on three-dimensional convex hull. [Citation Graph (, )][DBLP]

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