Masaru Takesue A Model of Pipelined Mutual Exclusion on Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP] Euro-Par, 2003, pp:917-922 [Conf]
Masaru Takesue Schemes for Reducing Communication Latency in Regular Computations on DSM Multiprocessors. [Citation Graph (0, 0)][DBLP] ICPP, 1998, pp:164-171 [Conf]
Masaru Takesue Software Queue-Based Algorithms for Pipelined Synchronization on Multiprocessors. [Citation Graph (0, 0)][DBLP] ICPP Workshops, 2003, pp:115-122 [Conf]
Masaru Takesue The Psi-Cube: A Bus-Based Cube-Type Network for High-Performance On-Chip Systems. [Citation Graph (0, 0)][DBLP] ICPP Workshops, 2005, pp:539-546 [Conf]
Masaru Takesue A Unified Resource Management and Execution Control Mechanism for Data Flow Machines. [Citation Graph (0, 0)][DBLP] ISCA, 1987, pp:90-97 [Conf]
Masaru Takesue A tampering protocol for reducing the coherence transactions in regular computation. [Citation Graph (0, 0)][DBLP] ISPAN, 1997, pp:465-471 [Conf]