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Yue Hao :
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Junping Wang , Yue Hao Short Critical Area Computational Method Using Mathematical Morphology. [Citation Graph (0, 0)][DBLP ] CIS (2), 2005, pp:796-803 [Conf ] Xiaohong Jiang , Susumu Horiguchi , Yue Hao Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core. [Citation Graph (0, 0)][DBLP ] DFT, 2000, pp:30-0 [Conf ] Tianxu Zhao , Xuchao Duan , Yue Hao , Peijun Ma Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a Chip. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:11-17 [Conf ] Tianxu Zhao , Yue Hao , Yongchang Jiao VLSI Yield Optimization Based on the Sub-Processing-Element Level Redundancy. [Citation Graph (0, 0)][DBLP ] DFT, 2000, pp:41-46 [Conf ] Tianxu Zhao , Yue Hao , Peijun Ma , Taifeng Chen Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model. [Citation Graph (0, 0)][DBLP ] DFT, 2001, pp:48-0 [Conf ] Hongxia Ren , Yue Hao Study on the degradation induced by donor interface state in deep-sub-micron grooved-gate P-channel MOSFET's. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:4, pp:597-604 [Journal ] Hongxia Liu , Yue Hao , Jiangang Zhu A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2002, v:42, n:7, pp:1037-1044 [Journal ] Ming-e Jing , Yue Hao , Jin-feng Zhang , Peijun Ma Efficient parametric yield optimization of VLSI circuit by uniform design sampling method. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2005, v:45, n:1, pp:155-162 [Journal ] Daoguang Liu , Siliu Xu , Kaicheng Li , Jin Zhang , Rongkan Liu , Yukui Liu , Zhengfan Zhang , Gangyi Hu , Yue Hao Growth and quality control of MBE-based SiGe-HBT for amplifier applications. [Citation Graph (0, 0)][DBLP ] Microelectronics Journal, 2003, v:34, n:5-8, pp:587-589 [Journal ] Search in 0.001secs, Finished in 0.002secs