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Jordi Cortadella: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jordi Cortadella, Gabriel Valiente
    A Relational View of Subgraph Isomorphism. [Citation Graph (0, 0)][DBLP]
    RelMiCS, 2000, pp:45-54 [Conf]
  2. Josep Carmona, Jordi Cortadella, Victor Khomenko, Alexandre Yakovlev
    Synthesis of Asynchronous Hardware from Petri Nets. [Citation Graph (0, 0)][DBLP]
    Lectures on Concurrency and Petri Nets, 2003, pp:345-401 [Conf]
  3. Josep Carmona, Jordi Cortadella, Enric Pastor
    Synthesis of Reactive Systems: Application to Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:108-151 [Conf]
  4. Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. [Citation Graph (0, 0)][DBLP]
    ACSD, 1998, pp:152-0 [Conf]
  5. Josep Carmona, Jordi Cortadella, Enric Pastor
    A structural encoding technique for the synthesis of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ACSD, 2001, pp:157-166 [Conf]
  6. Robert Clarisó, Jordi Cortadella
    Verification of Concurrent Systems with Parametric Delays Using Octahedra. [Citation Graph (0, 0)][DBLP]
    ACSD, 2005, pp:122-131 [Conf]
  7. Jordi Cortadella
    Combining Structural and Symbolic Methods for the Verification of Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    ACSD, 1998, pp:2-7 [Conf]
  8. Jordi Cortadella, Kyller Costa Gorgônio, Fei Xia, Alexandre Yakovlev
    Automating Synthesis of Asynchronous Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    ACSD, 2005, pp:166-175 [Conf]
  9. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe
    Quasi-Static Scheduling for Concurrent Architectures. [Citation Graph (0, 0)][DBLP]
    ACSD, 2003, pp:29-40 [Conf]
  10. Robert Clarisó, Enric Rodríguez-Carbonell, Jordi Cortadella
    Derivation of Non-structural Invariants of Petri Nets Using Abstract Interpretation. [Citation Graph (0, 0)][DBLP]
    ICATPN, 2005, pp:188-207 [Conf]
  11. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    Hardware and Petri Nets: Application to Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    ICATPN, 2000, pp:1-15 [Conf]
  12. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
    Quasi-Static Scheduling of Independent Tasksfor Reactive Systems. [Citation Graph (0, 0)][DBLP]
    ICATPN, 2002, pp:80-100 [Conf]
  13. Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Coupling Asynchrony and Interrupts: Place Chart Nets. [Citation Graph (0, 0)][DBLP]
    ICATPN, 1997, pp:328-347 [Conf]
  14. Oriol Roig, Jordi Cortadella, Enric Pastor
    Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets. [Citation Graph (0, 0)][DBLP]
    Application and Theory of Petri Nets, 1995, pp:374-391 [Conf]
  15. Enric Pastor, Jordi Cortadella, Marco A. Peña
    Structural Methods to Improve the Symbolic Analysis of Petri Nets. [Citation Graph (0, 0)][DBLP]
    ICATPN, 1999, pp:26-45 [Conf]
  16. Enric Pastor, Oriol Roig, Jordi Cortadella, Rosa M. Badia
    Petri Net Analysis Using Boolean Manipulation. [Citation Graph (0, 0)][DBLP]
    Application and Theory of Petri Nets, 1994, pp:416-435 [Conf]
  17. Robert Clarisó, Jordi Cortadella
    Verification of timed circuits with symbolic delays. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:628-633 [Conf]
  18. Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
    T8: Logic Design of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:26-30 [Conf]
  19. Gianluca Cornetta, Jordi Cortadella
    A Multi-Radix Approach to Asynchronous Division. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:25-0 [Conf]
  20. Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou
    Handshake Protocols for De-Synchronization. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:149-158 [Conf]
  21. Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev
    Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:240-253 [Conf]
  22. Alexander Taubin, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno
    Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:36-0 [Conf]
  23. Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev
    Formal Verification of Safety Properties in Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:2-11 [Conf]
  24. Oriol Roig, Jordi Cortadella, Enric Pastor
    Hierarchical gate-level verification of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:128-137 [Conf]
  25. Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, Luciano Lavagno
    Partial order based approach to synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:254-0 [Conf]
  26. Michael Kishinevsky, Jordi Cortadella, Bill Grundmann, Sava Krstic, John O'Leary
    Synchronous Elastic Circuits. [Citation Graph (0, 0)][DBLP]
    CSR, 2006, pp:3-5 [Conf]
  27. David Bañeres, Jordi Cortadella, Michael Kishinevsky
    A recursive paradigm to solve Boolean relations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:416-421 [Conf]
  28. Josep Carmona, Jordi Cortadella
    State encoding of large asynchronous controllers. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:939-944 [Conf]
  29. Jordi Cortadella, Michael Kishinevsky, Bill Grundmann
    Synthesis of synchronous elastic architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:657-662 [Conf]
  30. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:63-66 [Conf]
  31. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
    Task generation and compile-time scheduling for mixed data-control embedded software. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:489-494 [Conf]
  32. Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev
    Asynchronous Interface Specification, Analysis and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:2-7 [Conf]
  33. Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:110-115 [Conf]
  34. Oriol Roig, Jordi Cortadella, Marco A. Peña, Enric Pastor
    Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:620-625 [Conf]
  35. Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella
    Synthesis of Speed-Independent Circuits from STG-Unfolding Segment. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:16-21 [Conf]
  36. Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
    CAD Directions for High Performance Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:116-121 [Conf]
  37. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou
    From Synchronous to Asynchronous: An Automatic Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1368-1369 [Conf]
  38. Enric Pastor, Jordi Cortadella
    Efficient Encoding Schemes for Symbolic Analysis of Petri Nets. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:790-795 [Conf]
  39. Marco A. Peña, Jordi Cortadella, Alexander B. Smirnov, Enric Pastor
    A Case Study for the Verification of Complex Timed Circuits: IPCMOS. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:44-53 [Conf]
  40. Fermín Sánchez, Jordi Cortadella
    RESIS: A New Methodology for Register Optimization in Software Pipelining. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:824-832 [Conf]
  41. Josep Carmona, Jordi Cortadella
    Input/Output Compatibility of Reactive Systems. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:360-377 [Conf]
  42. Sava Krstic, Jordi Cortadella, Michael Kishinevsky, John O'Leary
    Synchronous Elastic Networks. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:19-30 [Conf]
  43. David Bañeres, Jordi Cortadella, Michael Kishinevsky
    Dominator-based partitioning for delay optimization. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:67-72 [Conf]
  44. Gianluca Cornetta, Jordi Cortadella
    A Radix-16 SRT Division Unit with Speculation of the Quotient Digits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:74-77 [Conf]
  45. Enric Pastor, Jordi Cortadella, Oriol Roig
    A new look at the conditions for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:230-0 [Conf]
  46. Jordi Cortadella, José A. B. Fortes, Edward A. Lee
    Design and Prototyping of Digital Signal Processing (DSP) Systems: Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:56-57 [Conf]
  47. Josep Carmona, Jordi Cortadella
    ILP Models for the Synthesis of Asynchronous Control Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:818-826 [Conf]
  48. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens
    Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:324-331 [Conf]
  49. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:220-227 [Conf]
  50. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems: application to timing optimization of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:324-331 [Conf]
  51. Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Synthesizing Petri nets from state-based models. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:164-171 [Conf]
  52. Enric Pastor, Jordi Cortadella
    Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:250-254 [Conf]
  53. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev
    What is the cost of delay insensitivity? [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:316-323 [Conf]
  54. Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky
    Performance analysis of concurrent systems with early evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:448-455 [Conf]
  55. Josep Carmona, Jordi Cortadella, Yousuke Takada, Ferdinand Peper
    From molecular interactions to gates: a systematic approach. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:891-898 [Conf]
  56. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou
    Coping with The Variability of Combinational Logic Delays. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:505-508 [Conf]
  57. Enric Pastor, Jordi Cortadella
    An Efficient Unique State Coding Algorithm for Signal Transition Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:174-177 [Conf]
  58. Enric Musoll, Jordi Cortadella
    High-level synthesis techniques for reducing the activity of functional units. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:99-104 [Conf]
  59. Enric Musoll, Tomás Lang, Jordi Cortadella
    Exploiting the locality of memory references to reduce the address bus energy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:202-207 [Conf]
  60. Enric Musoll, Jordi Cortadella
    Scheduling and resource binding for low power. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:104-109 [Conf]
  61. Jordi Cortadella
    Bi-Decomposition and Tree-Height Reduction for Timing Optimization. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:233-238 [Conf]
  62. Robert Clarisó, Jordi Cortadella
    The Octahedron Abstract Domain. [Citation Graph (0, 0)][DBLP]
    SAS, 2004, pp:312-327 [Conf]
  63. Peter A. Beerel, Jordi Cortadella, Alex Kondratyev
    Bridging the Gap between Asynchronous Design and Designers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:18-20 [Conf]
  64. Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
    Logic Design of Asynchronous Circuits (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:26-0 [Conf]
  65. Nilesh Modi, Jordi Cortadella
    Boolean Decomposition Using Two-literal Divisors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:765-768 [Conf]
  66. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Yosinori Watanabe
    Quasi-static Scheduling for Concurrent Architectures. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2004, v:62, n:2, pp:171-196 [Journal]
  67. Josep Carmona, Jordi Cortadella, Enric Pastor
    A structural encoding technique for the synthesis of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2002, v:50, n:2, pp:135-154 [Journal]
  68. Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Jordi Cortadella, Luciano Lavagno
    The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 1998, v:8, n:1, pp:67-118 [Journal]
  69. Fermín Sánchez, Jordi Cortadella
    Reducing Register Pressure in Software Pipelining. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:265-279 [Journal]
  70. Robert Clarisó, Jordi Cortadella
    The octahedron abstract domain. [Citation Graph (0, 0)][DBLP]
    Sci. Comput. Program., 2007, v:64, n:1, pp:115-139 [Journal]
  71. Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Deriving Petri Nets for Finite Transition Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:859-882 [Journal]
  72. Jordi Cortadella, José M. Llabería
    Evaluation of A + B = K Conditions Without Carry Propagation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:11, pp:1484-1488 [Journal]
  73. Jordi Cortadella, Tomás Lang
    High-Radix Division and Square-Root with Speculation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:8, pp:919-931 [Journal]
  74. Enric Pastor, Jordi Cortadella, Oriol Roig
    Symbolic Analysis of Bounded Petri Nets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:5, pp:432-448 [Journal]
  75. Josep Carmona, José Manuel Colom, Jordi Cortadella, F. García-Vallés
    Synthesis of asynchronous controllers using integer linear programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1637-1651 [Journal]
  76. Jordi Cortadella
    Timing-driven logic bi-decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:675-685 [Journal]
  77. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:109-130 [Journal]
  78. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1221-1236 [Journal]
  79. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    A region-based theory for state assignment in speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:793-812 [Journal]
  80. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
    Quasi-static scheduling of independent tasks for reactive systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1492-1514 [Journal]
  81. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou
    Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1904-1921 [Journal]
  82. Enric Pastor, Jordi Cortadella, Alex Kondratyev, Oriol Roig
    Structural methods for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1108-1129 [Journal]
  83. Kyller Costa Gorgônio, Jordi Cortadella, Fei Xia
    A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    ICATPN, 2007, pp:144-163 [Conf]
  84. Jordi Cortadella, Michael Kishinevsky
    Synchronous Elastic Circuits with Early Evaluation and Token Counterflow. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:416-419 [Conf]
  85. David Bañeres, Jordi Cortadella, Michael Kishinevsky
    Layout-aware gate duplication and buffer insertion. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1367-1372 [Conf]
  86. Robert Clarisó, Jordi Cortadella
    Verification of Concurrent Systems with Parametric Delays Using Octahedra. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2007, v:78, n:1, pp:1-33 [Journal]
  87. Kyller Costa Gorgônio, Jordi Cortadella, Fei Xia, Alexandre Yakovlev
    Automating Synthesis of Asynchronous Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2007, v:78, n:1, pp:75-100 [Journal]
  88. Enric Musoll, Tomás Lang, Jordi Cortadella
    Working-zone encoding for reducing the energy in microprocessor address buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:568-572 [Journal]

  89. Scheduling Synchronous Elastic Designs. [Citation Graph (, )][DBLP]


  90. Time elastic digital systems and Petri Nets. [Citation Graph (, )][DBLP]


  91. Genet: A Tool for the Synthesis and Mining of Petri Nets. [Citation Graph (, )][DBLP]


  92. A Symbolic Algorithm for the Synthesis of Bounded Petri Nets. [Citation Graph (, )][DBLP]


  93. Division with speculation of quotient digits. [Citation Graph (, )][DBLP]


  94. A Region-Based Algorithm for Discovering Petri Nets from Event Logs. [Citation Graph (, )][DBLP]


  95. Divide-and-Conquer Strategies for Process Mining. [Citation Graph (, )][DBLP]


  96. Speculation in elastic systems. [Citation Graph (, )][DBLP]


  97. Enabling adaptability through elastic clocks. [Citation Graph (, )][DBLP]


  98. Retiming and recycling for elastic systems with early evaluation. [Citation Graph (, )][DBLP]


  99. Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. [Citation Graph (, )][DBLP]


  100. Variable-latency design by function speculation. [Citation Graph (, )][DBLP]


  101. Automatic microarchitectural pipelining. [Citation Graph (, )][DBLP]


  102. Timing-driven N-way decomposition. [Citation Graph (, )][DBLP]


  103. A general model for performance optimization of sequential systems. [Citation Graph (, )][DBLP]


  104. Correct-by-construction microarchitectural pipelining. [Citation Graph (, )][DBLP]


  105. Performance optimization of elastic systems using buffer resizing and buffer insertion. [Citation Graph (, )][DBLP]


  106. Multi-level clustering for clock skew optimization. [Citation Graph (, )][DBLP]


  107. A performance analytical model for Network-on-Chip with constant service time routers. [Citation Graph (, )][DBLP]


  108. Process Mining Meets Abstract Interpretation. [Citation Graph (, )][DBLP]


  109. Hardware Synthesis for Asynchronous Communications Mechanisms. [Citation Graph (, )][DBLP]


  110. Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. [Citation Graph (, )][DBLP]


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