The SCEAS System
Navigation Menu

Search the dblp DataBase


Elias Kougianos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cheryl A. Kincaid, Saraju P. Mohanty, Armin R. Mikler, Elias Kougianos, Brandon Parker
    A High Performance ASIC for Cellular Automata (CA) Applications. [Citation Graph (0, 0)][DBLP]
    ICIT, 2006, pp:289-290 [Conf]
  2. Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos
    Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1191-1196 [Conf]
  3. Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos
    A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:431-437 [Conf]
  4. Saraju P. Mohanty, Guturu Parthasarathy, Elias Kougianos, Nishikanta Pati
    A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction. [Citation Graph (0, 0)][DBLP]
    ISM, 2006, pp:153-160 [Conf]
  5. Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos
    Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:564-569 [Conf]
  6. Saraju P. Mohanty, Elias Kougianos
    Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:83-88 [Conf]
  7. Saraju P. Mohanty, Elias Kougianos
    Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:577-582 [Conf]
  8. Elias Kougianos, Saraju P. Mohanty
    Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:195-200 [Conf]
  9. Elias Kougianos, Saraju P. Mohanty
    Effective tunneling capacitance: a new metric to quantify transient gate leakage current. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  10. Saraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee
    Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  11. A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. [Citation Graph (, )][DBLP]

  12. Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. [Citation Graph (, )][DBLP]

  13. Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates. [Citation Graph (, )][DBLP]

  14. A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs. [Citation Graph (, )][DBLP]

  15. Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. [Citation Graph (, )][DBLP]

  16. VLSI architectures of perceptual based video watermarking for real-time copyright protection. [Citation Graph (, )][DBLP]

  17. Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. [Citation Graph (, )][DBLP]

  18. A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. [Citation Graph (, )][DBLP]

  19. A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. [Citation Graph (, )][DBLP]

  20. A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO. [Citation Graph (, )][DBLP]

Search in 0.019secs, Finished in 0.021secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002