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Daniel K. Beece: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. George Almási, George S. Almasi, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David Heidel, Philip Heidelberger, Lorraine Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh
    Blue Gene/L, a System-On-A-Chip. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2002, pp:349-0 [Conf]
  2. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
    SLS - a fast switch level simulator for verification and fault coverage analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:164-170 [Conf]
  3. Daniel K. Beece, George Deibert, Georgina Papp, Frank Villante
    The IBM Engineering Verification Engine. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:218-224 [Conf]
  4. Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
    Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:710-711 [Conf]
  5. Kenneth L. Shepard, S. Carey, Daniel K. Beece, Robert F. Hatch, Gregory A. Northrop
    Design Methodology for the High-Performance G4 S/390. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:232-240 [Conf]
  6. Narasimha R. Adiga, George Almási, George S. Almasi, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, W. Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David Heidel, Philip Heidelberger, Lorraine Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Y. Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, C. T. Li, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, M. Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates
    An overview of the BlueGene/L Supercomputer. [Citation Graph (0, 0)][DBLP]
    SC, 2002, pp:1-22 [Conf]
  7. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman
    Using a Hardware Simulation Engine for Custom MOS Structured Designs. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1984, v:28, n:5, pp:564-571 [Journal]
  8. Michael E. Wazlowski, Narasimha R. Adiga, Daniel K. Beece, Ralph Bellofatto, Matthias A. Blumrich, Dong Chen, Marc Boris Dombrowa, Alan Gara, Mark Giampapa, Ruud A. Haring, Philip Heidelberger, Dirk Hoenicke, Ben J. Nathanson, Martin Ohmacht, Robert Sharrar, Sarabjeet Singh, Burkhard D. Steinmacher-Burow, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, Pavlos Vranas
    Verification strategy for the Blue Gene/L chip. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2005, v:49, n:2-3, pp:303-318 [Journal]
  9. Frances E. Allen, George S. Almasi, Wanda Andreoni, Daniel K. Beece, Bruce J. Berne, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Paul Coteus, Paul Crumley, Alessandro Curioni, Monty Denneau, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Bruce M. Fleischer, Christos J. Georgiou, Robert S. Germain, Mark Giampapa, Donna L. Gresh, Manish Gupta, Ruud A. Haring, C. T. Howard Ho, Peter H. Hochschild, Susan Flynn Hummel, Tiziana Jonas, Derek Lieber, Glenn J. Martyna, Kiran K. Maturu, José E. Moreira, Dennis M. Newns, Matthew Newton, Robert Philhower, Thomas Picunko, Jed Pitera, Michael Pitman, Rick A. Rand, Ajay K. Royyuru, Valentina Salapura, Alda Sanomiya, Rahul S. Shah, Yuk Yin Sham, Sarabjeet Singh, Marc Snir, Frank Suits, Richard A. Swetz, William C. Swope, Nagesh K. Vishnumurthy, T. J. Christopher Ward, Henry S. Warren Jr., Ruhong Zhou
    Blue Gene: A vision for protein science using a petaflop supercomputer. [Citation Graph (0, 0)][DBLP]
    IBM Systems Journal, 2001, v:40, n:2, pp:310-327 [Journal]
  10. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
    SLS-a fast switch-level simulator [for MOS]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:838-849 [Journal]
  11. Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett
    First-Order Incremental Block-Based Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2170-2180 [Journal]

  12. Transistor sizing of custom high-performance digital circuits with parametric yield considerations. [Citation Graph (, )][DBLP]


  13. The EVE companion simulator. [Citation Graph (, )][DBLP]


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