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Luis Ceze: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. George Almási, George S. Almasi, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David Heidel, Philip Heidelberger, Lorraine Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh
    Blue Gene/L, a System-On-A-Chip. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2002, pp:349-0 [Conf]
  2. George Almási, Ralph Bellofatto, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Crumley, C. Christopher Erway, Joseph Gagliano, Derek Lieber, Xavier Martorell, José E. Moreira, Alda Sanomiya, Karin Strauss
    An Overview of the Blue Gene/L System Software Organization. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2003, pp:543-555 [Conf]
  3. Calin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr.
    Evaluation of a Multithreaded Architecture for Cellular Computing. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:311-322 [Conf]
  4. Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
    Thread-Level Speculation on a CMP can be energy efficient. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:219-228 [Conf]
  5. Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas
    Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:179-188 [Conf]
  6. Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval
    Bulk Disambiguation of Speculative Threads in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:227-238 [Conf]
  7. James Tuck, Luis Ceze, Josep Torrellas
    Scalable Cache Miss Handling for High Memory-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:409-422 [Conf]
  8. Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas
    POSH: a TLS compiler that exploits program structure. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2006, pp:158-167 [Conf]
  9. Christoph von Praun, Luis Ceze, Calin Cascaval
    Implicit parallelism with ordered transactions. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:79-89 [Conf]
  10. Narasimha R. Adiga, George Almási, George S. Almasi, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, W. Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David Heidel, Philip Heidelberger, Lorraine Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Y. Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, C. T. Li, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, M. Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates
    An overview of the BlueGene/L Supercomputer. [Citation Graph (0, 0)][DBLP]
    SC, 2002, pp:1-22 [Conf]
  11. Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
    Energy-Efficient Thread-Level Speculation. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:80-91 [Journal]
  12. George Almási, Ralph Bellofatto, José R. Brunheroto, Calin Cascaval, José G. Castaños, Paul Crumley, C. Christopher Erway, Derek Lieber, Xavier Martorell, José E. Moreira, Ramendra K. Sahoo, Alda Sanomiya, Luis Ceze, Karin Strauss
    An Overview Of The Bluegene/L System Software Organization. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 2003, v:13, n:4, pp:561-574 [Journal]
  13. Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau
    CAVA: Using checkpoint-assisted value prediction to hide L2 misses. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:2, pp:182-208 [Journal]
  14. Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas
    BulkSC: bulk enforcement of sequential consistency. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:278-289 [Conf]

  15. SoftSig: software-exposed hardware signatures for code analysis and optimization. [Citation Graph (, )][DBLP]


  16. Concurrency control with data coloring. [Citation Graph (, )][DBLP]


  17. DMP: deterministic shared memory multiprocessing. [Citation Graph (, )][DBLP]


  18. CoreDet: a compiler and runtime system for deterministic multithreaded execution. [Citation Graph (, )][DBLP]


  19. Colorama: Architectural Support for Data-Centric Synchronization. [Citation Graph (, )][DBLP]


  20. DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently. [Citation Graph (, )][DBLP]


  21. Atom-Aid: Detecting and Surviving Atomicity Violations. [Citation Graph (, )][DBLP]


  22. Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-races. [Citation Graph (, )][DBLP]


  23. ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations. [Citation Graph (, )][DBLP]


  24. Finding concurrency bugs with context-aware communication graphs. [Citation Graph (, )][DBLP]


  25. Two hardware-based approaches for deterministic multiprocessor replay. [Citation Graph (, )][DBLP]


  26. The Bulk Multicore architecture for improved programmability. [Citation Graph (, )][DBLP]


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