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Publications of Author

1. Ludovic Alvado, Sylvain Saïghi, Jean Tomas, Sylvie Renaud-Le Masson
   An Exponential-Decay Synapse Integrated Circuit for Bio-inspired Neural Networks. [Citation Graph (0, 0)][DBLP]
   IWANN (1), 2003, pp:670-677 [Conf]
   
2. Sylvain Saïghi, Jean Tomas, Yannick Bornat, Sylvie Renaud
   A Neuromimetic Integrated Circuit for Interactive Real-Time Simulation. [Citation Graph (0, 0)][DBLP]
   IWINAC (2), 2005, pp:338-346 [Conf]
   
3. Jean Tomas, Yann Deval, Jean-Baptiste Begueret, P. Fouillat, J. L. Aucouturier
   A New Industrial Approach Compatible With Microelectronics Education: Application to an RF System Design. [Citation Graph (0, 0)][DBLP]
   MSE, 1999, pp:37-38 [Conf]
   
4. Ludovic Alvado, Jean Tomas, Sylvain Saïghi, Sylvie Renaud, Thierry Bal, Alain Destexhe, Gwendal Le Masson
   Hardware computation of conductance-based neuron models. [Citation Graph (0, 0)][DBLP]
   Neurocomputing, 2004, v:58, n:, pp:109-115 [Journal]
   
5. Quan Zou, Yannick Bornat, Jean Tomas, Sylvie Renaud, Alain Destexhe
   Real-time simulations of networks of Hodgkin-Huxley neurons using analog circuits. [Citation Graph (0, 0)][DBLP]
   Neurocomputing, 2006, v:69, n:10-12, pp:1137-1140 [Journal]
   
6. Sylvie Renaud-Le Masson, Gwendal Le Masson, Ludovic Alvado, Sylvain Saïghi, Jean Tomas
   A neural simulation system based on biologically realistic electronic neurons. [Citation Graph (0, 0)][DBLP]
   Inf. Sci., 2004, v:161, n:1-2, pp:57-69 [Journal]
   
7. Sylvie Renaud, Jean Tomas, Yannick Bornat, Adel Daouzli, Sylvain Saïghi
   Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:3355-3358 [Conf]
   
8. Sylvain Saïghi, Yannick Bornat, Jean Tomas, Sylvie Renaud
   Neuromimetic ICs and system for parameters extraction in biological neuron models. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
9. 
   Adjusting the neurons models in neuromimetic ICs using the voltage-clamp technique. [Citation Graph (, )][DBLP]
   
   
10. 
    A CMOS Resizing Methodology for Analog Circuits. [Citation Graph (, )][DBLP]