|
Search the dblp DataBase
Thomas Zeiser:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Thomas Pohl, Frank Deserno, Nils Thürey, Ulrich Rüde, Peter Lammers, Gerhard Wellein, Thomas Zeiser
Performance Evaluation of Parallel Large-Scale Lattice Boltzmann Applications on Three Supercomputing Architectures. [Citation Graph (0, 0)][DBLP] SC, 2004, pp:21- [Conf]
Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization. [Citation Graph (, )][DBLP]
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers. [Citation Graph (, )][DBLP]
The world's fastest CPU and SMP node: Some performance results from the NEC SX-9. [Citation Graph (, )][DBLP]
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers [Citation Graph (, )][DBLP]
RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks [Citation Graph (, )][DBLP]
Search in 0.002secs, Finished in 0.002secs
|