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Avadis Tevanian: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michael J. Accetta, Robert V. Baron, William J. Bolosky, David B. Golub, Richard F. Rashid, Avadis Tevanian, Michael Young
    Mach: A New Kernel Foundation for UNIX Development. [Citation Graph (2, 0)][DBLP]
    USENIX Summer, 1986, pp:93-113 [Conf]
  2. Michael Young, Avadis Tevanian, Richard F. Rashid, David B. Golub, Jeffrey L. Eppinger, Jonathan Chew, William J. Bolosky, David L. Black, Robert V. Baron
    The Duality of Memory and Communication in the Implementation of a Multiprocessor Operating System. [Citation Graph (1, 0)][DBLP]
    SOSP, 1987, pp:63-76 [Conf]
  3. Avadis Tevanian, Richard F. Rashid, Michael Young, David B. Golub, Mary R. Thompson, William J. Bolosky, Richard Sanzi
    A UNIX Interface for Shared Memory and Memory Mapped Files Under Mach. [Citation Graph (1, 0)][DBLP]
    USENIX Summer, 1987, pp:53-68 [Conf]
  4. Richard F. Rashid, Avadis Tevanian, Michael Young, David B. Golub, Robert V. Baron, David L. Black, William J. Bolosky, Jonathan Chew
    Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1987, pp:31-39 [Conf]
  5. David L. Black, Avadis Tevanian, David B. Golub, Michael W. Young
    Locking and Reference Counting in the Mach Kernel. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1991, pp:167-173 [Conf]
  6. David L. Black, David B. Golub, Karl Hauth, Avadis Tevanian, Richard Sanzi
    The Mach Exception Handling Facilty. [Citation Graph (0, 0)][DBLP]
    Workshop on Parallel and Distributed Debugging, 1988, pp:45-56 [Conf]
  7. Avadis Tevanian, Trey Matteson, David Jaffe, Bryan Yamamoto
    Software Technology at NeXT Computer. [Citation Graph (0, 0)][DBLP]
    USENIX Summer, 1991, pp:313- [Conf]
  8. Richard F. Rashid, Avadis Tevanian, Michael Young, David B. Golub, Robert V. Baron, David L. Black, William J. Bolosky, Jonathan Chew
    Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:8, pp:896-907 [Journal]

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