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Ulrich Golze :
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Volker Henkel , Ulrich Golze RISCE - A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:465-470 [Conf ] Nico Kasprzyk , Andreas Koch , Ulrich Golze , Michael Rock An Improved Intermediate Representation for Datapath Generation. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:88-94 [Conf ] Tamer Çatalkaya , Ulrich Golze Entwicklung multimedialer Lernprogramme im Chip-Entwurf für und als Teil der Lehre. [Citation Graph (0, 0)][DBLP ] Workshop Multimedia-Systeme, GI Jahrestagung, 1998, pp:9-18 [Conf ] Tamer Çatalkaya , Ulrich Golze Efficient Production of Computer-Based Training in Chip Desig. [Citation Graph (0, 0)][DBLP ] MSE, 2001, pp:12-13 [Conf ] Helge Böhme , Ulrich Golze Lightweight Firm Real-Time Extensions for Low Memory Profile Java Systems. [Citation Graph (0, 0)][DBLP ] OTM Workshops, 2004, pp:303-314 [Conf ] Ulrich Golze Lokale und globale Synchronisation. [Citation Graph (0, 0)][DBLP ] Elektronische Informationsverarbeitung und Kybernetik, 1979, v:15, n:8/9, pp:435-443 [Journal ] Ulrich Golze , Lutz Priese Petri Net Implementations by a Universal Cell Space [Citation Graph (0, 0)][DBLP ] Information and Control, 1982, v:53, n:1/2, pp:121-138 [Journal ] Ulrich Golze (A-)Synchronous (Non-)Deterministic Cell Spaces Simulating Each Other. [Citation Graph (0, 0)][DBLP ] J. Comput. Syst. Sci., 1978, v:17, n:2, pp:176-193 [Journal ] Hans Georg Carstens , Ulrich Golze Recursive Paths in Cross-Connected Trees and an Application to Cell Spaces. [Citation Graph (0, 0)][DBLP ] Mathematical Systems Theory, 1981, v:15, n:1, pp:29-37 [Journal ] Search in 0.008secs, Finished in 0.010secs