The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Piero Vicini: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. R. Ammendola, M. Guagnelli, G. Mazza, F. Palombi, R. Petronzio, Davide Rossetti, A. Salamon, Piero Vicini
    APENet: a high speed, low latency 3D interconnect network. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2004, pp:481- [Conf]
  2. Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini
    SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:167-172 [Conf]
  3. F. Aglietti, A. Bartolini, C. Battista, S. Cabasino, M. Cosimi, A. Michelotti, A. Monello, Emanuele Panizzi, Pier Stanislao Paolucci, W. Rinaldi, Davide Rossetti, Hubert Simma, M. Torelli, Piero Vicini, Nicola Cabibbo, E. Centurioni, W. Errico, F. Laico, G. Magazzù, Raffaele Tripiccione
    The Teraflop Parallel Computer APEmille. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1997, pp:991-993 [Conf]
  4. François Bodin, Philippe Boucaud, Nicola Cabibbo, F. Di Carlo, R. De Pietri, F. Di Renzo, H. Kaldass, Alessandro Lonardo, Maxim Lukyanov, Sergio de Luca, Jacques Micheli, Vincent Morenas, Norbert Paschedag, Olivier Pene, Dirk Pleiter, Federico Rapuano, L. Sartori, Sebastiano Fabio Schifano, Hubert Simma, Raffaele Tripiccione, Piero Vicini
    apeNEXT: a Multi-TFlops Computer for Elementary Particle Physics. [Citation Graph (0, 0)][DBLP]
    PARCO, 2003, pp:355-362 [Conf]
  5. Francesco Belletti, Sebastiano Fabio Schifano, Raffaele Tripiccione, François Bodin, Philippe Boucaud, Jacques Micheli, Olivier Pene, Nicola Cabibbo, Sergio de Luca, Alessandro Lonardo, Davide Rossetti, Piero Vicini, Maxim Lukyanov, Laurent Morin, Norbert Paschedag, Hubert Simma, Vincent Morenas, Dirk Pleiter, Federico Rapuano
    Computing for LQCD: apeNEXT. [Citation Graph (0, 0)][DBLP]
    Computing in Science and Engineering, 2006, v:8, n:1, pp:18-29 [Journal]

  6. Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002