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Lothar Thiele: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jürgen Teich, Lothar Thiele, Li Zhang
    Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:131-144 [Conf]
  2. Alexander Maxiaguine, Simon Künzli, Samarjit Chakraborty, Lothar Thiele
    Rate analysis for streaming applications with on-chip buffer constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:131-136 [Conf]
  3. Ernesto Wandeler, Lothar Thiele
    Abstracting functionality for modular performance analysis of hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:697-702 [Conf]
  4. Ernesto Wandeler, Lothar Thiele
    Optimal TDMA time slot and cycle length allocation for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:479-484 [Conf]
  5. Alexander Maxiaguine, Samarjit Chakraborty, Lothar Thiele
    DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:111-116 [Conf]
  6. Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    Scheduling hardware/software systems using symbolic techniques. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:173-177 [Conf]
  7. Jürgen Teich, Tobias Blickle, Lothar Thiele
    An evolutionary approach to system-level synthesis. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:167-172 [Conf]
  8. Dirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele
    Combining multiple models of computation for scheduling and allocation. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:9-13 [Conf]
  9. Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini
    SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:167-172 [Conf]
  10. Samarjit Chakraborty, Thomas Erlebach, Simon Künzli, Lothar Thiele
    Schedulability of event-driven code blocks in real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:616-621 [Conf]
  11. Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich
    Representation of Function Variants for Embedded System Optimization and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:517-522 [Conf]
  12. Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli
    A framework for evaluating design tradeoffs in packet processing architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:880-885 [Conf]
  13. Marco Laumanns, Lothar Thiele, Eckart Zitzler
    An Adaptive Scheme to Generate the Pareto Front Based on the Epsilon-Constraint Method. [Citation Graph (0, 0)][DBLP]
    Practical Approaches to Multi-Objective Optimization, 2005, pp:- [Conf]
  14. Lothar Thiele, Reinhard Wilhelm
    Abstracts Collection. [Citation Graph (0, 0)][DBLP]
    Design of Systems with Predictable Behaviour, 2004, pp:- [Conf]
  15. Lothar Thiele, Reinhard Wilhelm
    Design for Time-Predictability. [Citation Graph (0, 0)][DBLP]
    Design of Systems with Predictable Behaviour, 2004, pp:- [Conf]
  16. Samarjit Chakraborty, Simon Künzli, Lothar Thiele
    A General Framework for Analysing System Properties in Platform-Based Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10190-10195 [Conf]
  17. Samarjit Chakraborty, Lothar Thiele
    A New Task Model for Streaming Applications and Its Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:486-491 [Conf]
  18. Simon Künzli, Francesco Poletti, Luca Benini, Lothar Thiele
    Combining simulation and formal methods for system-level performance analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:236-241 [Conf]
  19. Alexander Maxiaguine, Simon Künzli, Lothar Thiele
    Workload Characterization Model for Tasks with Variable Execution Demand. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1040-1045 [Conf]
  20. Karsten Strehl, Lothar Thiele
    Interval Diagram Techniques for Symbolic Model Checking of Petri Nets. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:756-757 [Conf]
  21. Ernesto Wandeler, Alexander Maxiaguine, Lothar Thiele
    Performance analysis of greedy shapers in real-time systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:444-449 [Conf]
  22. Stefan Bleuler, Marco Laumanns, Lothar Thiele, Eckart Zitzler
    PISA: A Platform and Programming Language Independent Interface for Search Algorithms. [Citation Graph (0, 0)][DBLP]
    EMO, 2003, pp:494-508 [Conf]
  23. Marco Laumanns, Eckart Zitzler, Lothar Thiele
    On the Effects of Archiving, Elitism, and Density Based Selection in Evolutionary Multi-objective Optimization. [Citation Graph (0, 0)][DBLP]
    EMO, 2001, pp:181-196 [Conf]
  24. Eckart Zitzler, Dimo Brockhoff, Lothar Thiele
    The Hypervolume Indicator Revisited: On the Design of Pareto-compliant Indicators Via Weighted Integration. [Citation Graph (0, 0)][DBLP]
    EMO, 2006, pp:862-876 [Conf]
  25. Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Alexander Maxiaguine, Jonas Greutert
    Embedded Software in Network Processors - Models and Algorithms. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2001, pp:416-434 [Conf]
  26. Ernesto Wandeler, Lothar Thiele
    Real-time interfaces for interface-based design of real-time systems with fixed priority scheduling. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:80-89 [Conf]
  27. Lothar Thiele, Ernesto Wandeler, Nikolay Stoimenov
    Real-time interfaces for composing real-time systems. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:34-43 [Conf]
  28. Philipp Blum, Lothar Thiele
    Trace-based evaluation of clock synchronization algorithms for wireless loudspeakers. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:7-12 [Conf]
  29. Matthias Dyer, Jan Beutel, Thomas Kalt, Patrice Oehen, Lothar Thiele, Kevin Martin, Philipp Blum
    Deployment Support Network. [Citation Graph (0, 0)][DBLP]
    EWSN, 2007, pp:195-211 [Conf]
  30. Jan Beutel, Oliver Kasten, Friedemann Mattern, Kay Römer, Frank Siegemund, Lothar Thiele
    Prototyping Wireless Sensor Network Applications with BTnodes. [Citation Graph (0, 0)][DBLP]
    EWSN, 2004, pp:323-338 [Conf]
  31. Luca Negri, Lothar Thiele
    Power Management for Bluetooth Sensor Networks. [Citation Graph (0, 0)][DBLP]
    EWSN, 2006, pp:196-211 [Conf]
  32. Matthias Dyer, Marco Platzner, Lothar Thiele
    Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:342-344 [Conf]
  33. Philipp W. Kutter, Daniel Schweizer, Lothar Thiele
    Integrating Domain Specific Language Design in the Software Life Cycle. [Citation Graph (0, 0)][DBLP]
    FM-Trends, 1998, pp:196-212 [Conf]
  34. Lothar Thiele
    Modular Performance Analysis of Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    FORMATS, 2005, pp:1- [Conf]
  35. Michael Eisenring, Marco Platzner, Lothar Thiele
    Communication Synthesis for Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:205-214 [Conf]
  36. Marco Laumanns, Lothar Thiele, Eckart Zitzler, Kalyanmoy Deb
    Archiving With Guaranteed Convergence And Diversity In Multi-objective Optimization. [Citation Graph (0, 0)][DBLP]
    GECCO, 2002, pp:439-447 [Conf]
  37. Eckart Zitzler, Marco Laumanns, Lothar Thiele, Carlos M. Fonseca, Viviane Grunert da Fonseca
    Why Quality Assessment Of Multiobjective Optimizers Is Difficult. [Citation Graph (0, 0)][DBLP]
    GECCO, 2002, pp:666-674 [Conf]
  38. Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele
    SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 2005, pp:693-697 [Conf]
  39. Uwe Schwiegelshohn, Lothar Thiele
    Periodic and Non-periodic Min-Max Equations. [Citation Graph (0, 0)][DBLP]
    ICALP, 1997, pp:379-389 [Conf]
  40. Karsten Strehl, Lothar Thiele
    Symbolic model checking of process networks using interval diagram techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:686-692 [Conf]
  41. Lothar Thiele
    Integral Design Representations for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:264- [Conf]
  42. Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState - an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:558-565 [Conf]
  43. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele
    Representation of process mode correlation for scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:54-61 [Conf]
  44. Jean-Paul Theis, Lothar Thiele
    POM: a processor model for image processing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:326-331 [Conf]
  45. Jean-Paul Theis, Lothar Thiele
    VLIW-Processors under Periodic Real Time Constraints. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:191-0 [Conf]
  46. Tobias Blickle, Lothar Thiele
    A Mathematical Analysis of Tournament Selection. [Citation Graph (0, 0)][DBLP]
    ICGA, 1995, pp:9-16 [Conf]
  47. Uwe Schwiegelshohn, Lothar Thiele
    On the Systolic Detection of Shortest Routes. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:762-764 [Conf]
  48. Jan Beutel, Matthias Dyer, Lennart Meier, Lothar Thiele
    Scalable topology control for deployment-support networks. [Citation Graph (0, 0)][DBLP]
    IPSN, 2005, pp:359-363 [Conf]
  49. Philipp Blum, Lennart Meier, Lothar Thiele
    Improved interval-based clock synchronization in sensor networks. [Citation Graph (0, 0)][DBLP]
    IPSN, 2004, pp:349-358 [Conf]
  50. Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele
    Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:129-136 [Conf]
  51. Jürgen Teich, Lothar Thiele, Edward A. Lee
    Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:156-161 [Conf]
  52. Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele
    Reconfigurable Hardware in Wearable Computing Nodes. [Citation Graph (0, 0)][DBLP]
    ISWC, 2002, pp:215-222 [Conf]
  53. Lennart Meier, Philipp Blum, Lothar Thiele
    Internal synchronization of drift-constraint clocks in ad-hoc sensor networks. [Citation Graph (0, 0)][DBLP]
    MobiHoc, 2004, pp:90-97 [Conf]
  54. Christian Heckler, Lothar Thiele
    Parallel Complexitiy of Lattice Basis Reduction and a Floating-Point Parallel Algorithm. [Citation Graph (0, 0)][DBLP]
    PARLE, 1993, pp:744-747 [Conf]
  55. Lennart Meier, Lothar Thiele
    Brief announcement: gradient clock synchronization in sensor networks. [Citation Graph (0, 0)][DBLP]
    PODC, 2005, pp:238- [Conf]
  56. Marco Laumanns, Lothar Thiele, Eckart Zitzler, Emo Welzl, Kalyanmoy Deb
    Running Time Analysis of Multi-objective Evolutionary Algorithms on a Simple Discrete Optimization Problem. [Citation Graph (0, 0)][DBLP]
    PPSN, 2002, pp:44-53 [Conf]
  57. Eckart Zitzler, Lothar Thiele
    Multiobjective Optimization Using Evolutionary Algorithms - A Comparative Case Study. [Citation Graph (0, 0)][DBLP]
    PPSN, 1998, pp:292-304 [Conf]
  58. Samarjit Chakraborty, Matthias Gries, Lothar Thiele
    Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2002, pp:45-54 [Conf]
  59. Ernesto Wandeler, Alexander Maxiaguine, Lothar Thiele
    Quantitative Characterization of Event Streams in Analysis of Hard Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time and Embedded Technology and Applications Symposium, 2004, pp:450-461 [Conf]
  60. Ernesto Wandeler, Lothar Thiele
    Characterizing Workload Correlations in Multi Processor Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time and Embedded Technology and Applications Symposium, 2005, pp:46-55 [Conf]
  61. Ernesto Wandeler, Lothar Thiele
    Interface-Based Design of Real-Time Systems with Hierarchical Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2006, pp:243-252 [Conf]
  62. Samarjit Chakraborty, Simon Künzli, Lothar Thiele
    Approximate Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 2002, pp:159-168 [Conf]
  63. Christoph Steiger, Herbert Walder, Marco Platzner, Lothar Thiele
    Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    RTSS, 2003, pp:224-235 [Conf]
  64. Samarjit Chakraborty, Yanhong Liu, Nikolay Stoimenov, Lothar Thiele, Ernesto Wandeler
    Interface-Based Rate Analysis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTSS, 2006, pp:25-34 [Conf]
  65. Jürgen Teich, Lothar Thiele
    Exact Partitioning of Affine Dependence Algorithms. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:135-153 [Conf]
  66. Ernesto Wandeler, Jörn W. Janneck, Edward A. Lee, Lothar Thiele
    Counting Interface Automata and their Application in Static Analysis of Actor Models. [Citation Graph (0, 0)][DBLP]
    SEFM, 2005, pp:106-116 [Conf]
  67. Wolfgang Backes, Uwe Schwiegelshohn, Lothar Thiele
    Analysis of Free Schedule in Periodic Graphs. [Citation Graph (0, 0)][DBLP]
    SPAA, 1992, pp:333-342 [Conf]
  68. Christian Heckler, Lothar Thiele
    A Parallel Lattice Basis Reduction for Mesh-Connected Processor Arrays and Parallel Complexity. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:400-407 [Conf]
  69. Ulrich Arzt, Daniela Merziger, Lothar Thiele
    Rekursive Prozeduraufrufe in VLSI-Occam. [Citation Graph (0, 0)][DBLP]
    Transputer-Anwender-Treffen, 1991, pp:108-115 [Conf]
  70. Samarjit Chakraborty, Thomas Erlebach, Lothar Thiele
    On the Complexity of Scheduling Conditional Real-Time Code. [Citation Graph (0, 0)][DBLP]
    WADS, 2001, pp:38-49 [Conf]
  71. Amela Prelic, Stefan Bleuler, Philip Zimmermann, Anja Wille, Peter Bühlmann, Wilhelm Gruissem, Lars Hennig, Lothar Thiele, Eckart Zitzler
    A systematic comparison and evaluation of biclustering methods for gene expression data. [Citation Graph (0, 0)][DBLP]
    Bioinformatics, 2006, v:22, n:9, pp:1122-1129 [Journal]
  72. Samarjit Chakraborty, Simon Künzli, Lothar Thiele, Andreas Herkersdorf, Patricia Sagmeister
    Performance evaluation of network processor architectures: combining simulation with analytical estimation. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2003, v:41, n:5, pp:641-665 [Journal]
  73. Michael Eisenring, Lothar Thiele, Eckart Zitzler
    Conflicting Criteria in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:51-59 [Journal]
  74. Alexander Maxiaguine, Samarjit Chakraborty, Simon Künzli, Lothar Thiele
    Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:368-377 [Journal]
  75. Tobias Blickle, Lothar Thiele
    A Comparison of Selection Schemes used in Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    Evolutionary Computation, 1996, v:4, n:4, pp:361-394 [Journal]
  76. Marco Laumanns, Lothar Thiele, Kalyanmoy Deb, Eckart Zitzler
    Combining Convergence and Diversity in Evolutionary Multiobjective Optimization. [Citation Graph (0, 0)][DBLP]
    Evolutionary Computation, 2002, v:10, n:3, pp:263-282 [Journal]
  77. Eckart Zitzler, Kalyanmoy Deb, Lothar Thiele
    Comparison of Multiobjective Evolutionary Algorithms: Empirical Results. [Citation Graph (0, 0)][DBLP]
    Evolutionary Computation, 2000, v:8, n:2, pp:173-195 [Journal]
  78. Ernesto Wandeler, Lothar Thiele
    Workload correlations in multi-processor hard real-time systems. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 2007, v:73, n:2, pp:207-224 [Journal]
  79. Uwe Schwiegelshohn, Lothar Thiele
    A Systolic Array for Cyclic-by-Rows Jacobi Algorithms. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1987, v:4, n:3, pp:334-340 [Journal]
  80. Uwe Schwiegelshohn, Lothar Thiele
    Linear Systolic Arrays for Matrix Comutations. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1989, v:7, n:1, pp:28-39 [Journal]
  81. Marco Laumanns, Lothar Thiele, Eckart Zitzler
    Running time analysis of evolutionary algorithms on a simplified multiobjective knapsack problem. [Citation Graph (0, 0)][DBLP]
    Natural Computing, 2004, v:3, n:1, pp:37-51 [Journal]
  82. Lothar Thiele, Jürgen Teich, Karsten Strehl
    Regular state machines. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2000, v:15, n:3-4, pp:265-300 [Journal]
  83. Christian Heckler, Lothar Thiele
    Computing Linear Data Dependencies in Nested Loop Programs. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1994, v:4, n:, pp:193-204 [Journal]
  84. Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, Gerhard Tröster
    The case for reconfigurable hardware in wearable computing. [Citation Graph (0, 0)][DBLP]
    Personal and Ubiquitous Computing, 2003, v:7, n:5, pp:299-308 [Journal]
  85. Lothar Thiele, Reinhard Wilhelm
    Design for Timing Predictability. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2004, v:28, n:2-3, pp:157-177 [Journal]
  86. Ernesto Wandeler, Alexander Maxiaguine, Lothar Thiele
    Quantitative Characterization of Event Streams in Analysis of Hard Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2005, v:29, n:2-3, pp:205-225 [Journal]
  87. Christian Heckler, Lothar Thiele
    Complexity Analysis of a Parallel Lattice Basis Reduction Algorithm. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1998, v:27, n:5, pp:1295-1302 [Journal]
  88. Matthias Anlauff, Samarjit Chakraborty, Philipp W. Kutter, Alfonso Pierantonio, Lothar Thiele
    Generating an action notation environment from Montages descriptions. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:4, pp:431-455 [Journal]
  89. Ernesto Wandeler, Lothar Thiele, Marcel Verhoef, Paul Lieverse
    System architecture evaluation using modular performance analysis: a case study. [Citation Graph (0, 0)][DBLP]
    STTT, 2006, v:8, n:6, pp:649-667 [Journal]
  90. Urs Anliker, Jan Beutel, Matthias Dyer, Rolf Enzler, Paul Lukowicz, Lothar Thiele, Gerhard Tröster
    A Systematic Approach to the Design of Distributed Wearable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:8, pp:1017-1033 [Journal]
  91. Uwe Schwiegelshohn, Lothar Thiele
    A Systolic Array for the Assignment Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:11, pp:1422-1425 [Journal]
  92. Karsten Strehl, Lothar Thiele
    Interval diagrams for efficient symbolic verification of processnetworks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:939-956 [Journal]
  93. Jürgen Teich, Lothar Thiele, Sundararajan Sriram, Michael Martin
    Performance analysis and optimization of mixed asynchronous synchronous systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:473-484 [Journal]
  94. Marco Laumanns, Lothar Thiele, Eckart Zitzler
    Running time analysis of multiobjective evolutionary algorithms on pseudo-Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2004, v:8, n:2, pp:170-182 [Journal]
  95. Eckart Zitzler, Lothar Thiele
    Multiobjective evolutionary algorithms: a comparative case study and the strength Pareto approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 1999, v:3, n:4, pp:257-271 [Journal]
  96. Eckart Zitzler, Lothar Thiele, Marco Laumanns, Carlos M. Fonseca, Viviane Grunert da Fonseca
    Performance assessment of multiobjective optimizers: an analysis and review. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2003, v:7, n:2, pp:117-132 [Journal]
  97. Marco Laumanns, Lothar Thiele, Eckart Zitzler
    An efficient, adaptive parameter variation scheme for metaheuristics based on the epsilon-constraint method. [Citation Graph (0, 0)][DBLP]
    European Journal of Operational Research, 2006, v:169, n:3, pp:932-942 [Journal]
  98. Lothar Thiele, Iuliana Bacivarov, Wolfgang Haid, Kai Huang
    Mapping Applications to Tiled Multiprocessor Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ACSD, 2007, pp:29-40 [Conf]
  99. Kai Huang, Lothar Thiele
    Performance analysis of multimedia applications using correlated streams. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:912-917 [Conf]
  100. Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini
    Adaptive power management in energy harvesting systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:773-778 [Conf]
  101. Clemens Moser, Davide Brunelli, Lothar Thiele, Luca Benini
    Lazy Scheduling for Energy Harvesting Sensor Nodes. [Citation Graph (0, 0)][DBLP]
    DIPES, 2006, pp:125-134 [Conf]
  102. Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState-an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:524-544 [Journal]
  103. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich
    SPI - a system model for heterogeneously specified embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:379-389 [Journal]

  104. Windowed FIFOs for FPGA-based Multiprocessor Systems. [Citation Graph (, )][DBLP]


  105. Combined approach to system level performance analysis of embedded systems. [Citation Graph (, )][DBLP]


  106. Complex task activation schemes in system level performance analysis. [Citation Graph (, )][DBLP]


  107. Worst-case response time analysis of resource access models in multi-core systems. [Citation Graph (, )][DBLP]


  108. 07101 Executive Summary -- Quantitative Aspects of Embedded Systems. [Citation Graph (, )][DBLP]


  109. 07101 Abstracts Collection -- Quantitative Aspects of Embedded Systems. [Citation Graph (, )][DBLP]


  110. Quality Assessment of Pareto Set Approximations. [Citation Graph (, )][DBLP]


  111. An Efficient Solar Energy Harvester for Wireless Sensor Nodes. [Citation Graph (, )][DBLP]


  112. Robust and Low Complexity Rate Control for Solar Powered Sensors. [Citation Graph (, )][DBLP]


  113. Reliable mode changes in real-time systems with fixed priority or EDF scheduling. [Citation Graph (, )][DBLP]


  114. An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]


  115. Cool MPSoC programming. [Citation Graph (, )][DBLP]


  116. Energy-efficient real-time task scheduling with temperature-dependent leakage. [Citation Graph (, )][DBLP]


  117. Worst case delay analysis for memory interference in multicore systems. [Citation Graph (, )][DBLP]


  118. ZeroCal: Automatic MAC Protocol Calibration. [Citation Graph (, )][DBLP]


  119. Real-Time Scheduling with Regenerative Energy. [Citation Graph (, )][DBLP]


  120. Cache-Aware Timing Analysis of Streaming Applications. [Citation Graph (, )][DBLP]


  121. Influence of different system abstractions on the performance analysis of distributed real-time systems. [Citation Graph (, )][DBLP]


  122. Cyclic dependencies in modular performance analysis. [Citation Graph (, )][DBLP]


  123. Performance analysis of distributed embedded systems. [Citation Graph (, )][DBLP]


  124. Modular performance analysis of cyclic dataflow graphs. [Citation Graph (, )][DBLP]


  125. Analytic real-time analysis and timed automata: a hybrid method for analyzing embedded real-time systems. [Citation Graph (, )][DBLP]


  126. Distributed Embedded Systems: Reconciling Computation, Communication and Resource Interaction. [Citation Graph (, )][DBLP]


  127. Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs. [Citation Graph (, )][DBLP]


  128. Exploiting Timed Automata for Conformance Testing of Power Measurements. [Citation Graph (, )][DBLP]


  129. Approximate Control Design for Solar Driven Sensor Nodes. [Citation Graph (, )][DBLP]


  130. Energy-Efficient Task Partition for Periodic Real-Time Tasks on Platforms with Dual Processing Elements. [Citation Graph (, )][DBLP]


  131. Energy minimization for periodic real-time tasks on heterogeneous processing units. [Citation Graph (, )][DBLP]


  132. Demo abstract: Operating a sensor network at 3500 m above sea level. [Citation Graph (, )][DBLP]


  133. PermaDAQ: A scientific instrument for precision sensing and data recovery in environmental extremes. [Citation Graph (, )][DBLP]


  134. Exploiting protocol models for generating feasible communication stack configurations. [Citation Graph (, )][DBLP]


  135. Expected system energy consumption minimization in leakage-aware DVS systems. [Citation Graph (, )][DBLP]


  136. Power management in energy harvesting embedded systems with discrete service levels. [Citation Graph (, )][DBLP]


  137. System Architecture Evaluation Using Modular Performance Analysis - A Case Study. [Citation Graph (, )][DBLP]


  138. Modeling structured event streams in system level performance analysis. [Citation Graph (, )][DBLP]


  139. Generating event traces based on arrival curves. [Citation Graph (, )][DBLP]


  140. SPAM: Set Preference Algorithm for Multiobjective Optimization. [Citation Graph (, )][DBLP]


  141. Defining and Optimizing Indicator-Based Diversity Measures in Multiobjective Search. [Citation Graph (, )][DBLP]


  142. Power-Aware Mapping of Probabilistic Applications onto Heterogeneous MPSoC Platforms. [Citation Graph (, )][DBLP]


  143. Proactive Speed Scheduling for Real-Time Tasks under Thermal Constraints. [Citation Graph (, )][DBLP]


  144. Thermal-Aware Global Real-Time Scheduling on Multicore Systems. [Citation Graph (, )][DBLP]


  145. Timing Analysis for TDMA Arbitration in Resource Sharing Systems. [Citation Graph (, )][DBLP]


  146. Reward Maximization for Embedded Systems with Renewable Energies. [Citation Graph (, )][DBLP]


  147. Task Partitioning and Platform Synthesis for Energy Efficiency. [Citation Graph (, )][DBLP]


  148. Energy-Efficient Speed Scheduling for Real-Time Tasks under Thermal Constraints. [Citation Graph (, )][DBLP]


  149. Feasibility Analysis of On-Line DVS Algorithms for Scheduling Arbitrary Event Streams. [Citation Graph (, )][DBLP]


  150. Composing Functional and State-Based Performance Models for Analyzing Heterogeneous Real-Time Systems. [Citation Graph (, )][DBLP]


  151. A Comprehensive Worst-Case Calculus for Wireless Sensor Networks with In-Network Processing. [Citation Graph (, )][DBLP]


  152. Adaptive Dynamic Power Management for Hard Real-Time Systems. [Citation Graph (, )][DBLP]


  153. Optimal service level allocation in environmentally powered embedded systems. [Citation Graph (, )][DBLP]


  154. Energy-efficient scheduling on homogeneous multiprocessor platforms. [Citation Graph (, )][DBLP]


  155. Generation and calibration of compositional performance analysis models for multi-processor systems. [Citation Graph (, )][DBLP]


  156. NoSE: efficient initialization of wireless sensor networks. [Citation Graph (, )][DBLP]


  157. Learning from sensor network data. [Citation Graph (, )][DBLP]


  158. The FlockLab testbed architecture. [Citation Graph (, )][DBLP]


  159. EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  160. Analysis, Comparison, and Optimization of Routing Protocols for Energy Harvesting Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  161. Scalably distributed SystemC simulation for embedded applications. [Citation Graph (, )][DBLP]


  162. Increasing the reliability of wireless sensor networks with a distributed testing framework. [Citation Graph (, )][DBLP]


  163. Analitic Performance Analysis of Distributed Embedded Systems. [Citation Graph (, )][DBLP]


  164. Periodic power management schemes for real-time event streams. [Citation Graph (, )][DBLP]


  165. A Preference-Based Evolutionary Algorithm for Multi-Objective Optimization. [Citation Graph (, )][DBLP]


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