The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Rainer Leupers: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rainer Leupers
    Instruction Scheduling for Clustered VLIW DSPs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:291-300 [Conf]
  2. Md. Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers
    Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:154-160 [Conf]
  3. Rainer Leupers
    Register allocation for common subexpressions in DSP data paths. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:235-240 [Conf]
  4. Rainer Leupers, Anupam Basu, Peter Marwedel
    Optimized Array Index Computation in DSP Programs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:87-92 [Conf]
  5. Rainer Leupers, Johann Elste, Birger Landwehr
    Generation of Interpretive and Compiled Instruction Set Simulators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:339-342 [Conf]
  6. Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel
    Optimized address assignment for DSPs with SIMD memory accesses. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:415-420 [Conf]
  7. Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis, Rainer Leupers
    Compiler based exploration of DSP energy savings by SIMD operations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:838-841 [Conf]
  8. Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
    A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:280-285 [Conf]
  9. Rainer Leupers
    Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms. [Citation Graph (0, 0)][DBLP]
    CC, 2003, pp:290-302 [Conf]
  10. Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens
    A modular simulation framework for architectural exploration of on-chip interconnection networks. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:7-12 [Conf]
  11. Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
    Retargetable generation of TLM bus interfaces for MP-SoC platforms. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:249-254 [Conf]
  12. Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren
    Retargetable code optimization with SIMD instructions. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:148-153 [Conf]
  13. Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini
    SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:167-172 [Conf]
  14. Steven Bashford, Rainer Leupers
    Constraint Driven Code Selection for Fixed-Point DSPs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:817-822 [Conf]
  15. Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr
    A novel approach for flexible and consistent ADL-driven ASIP design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:717-722 [Conf]
  16. Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Fine-grained application source code profiling for ASIP design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:329-334 [Conf]
  17. Lorenz Ladage, Rainer Leupers
    Resistance Extraction using a Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:38-42 [Conf]
  18. Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
    A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:22-27 [Conf]
  19. Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr
    Instruction encoding synthesis for architecture exploration using hierarchical processor models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:262-267 [Conf]
  20. Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini
    An integrated open framework for heterogeneous MPSoC design space exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1145-1150 [Conf]
  21. Anupam Basu, Rainer Leupers, Peter Marwedel
    Register-Constrained Address Computation in DSP Programs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:929-930 [Conf]
  22. Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
    Processor/Memory Co-Exploration on Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10966-10973 [Conf]
  23. Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    C Compiler Retargeting Based on Instruction Semantics Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1150-1155 [Conf]
  24. Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, H. Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Automatic ADL-based operand isolation for embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:600-605 [Conf]
  25. Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    ASIP design and synthesis for non linear filtering in image processing. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:233-238 [Conf]
  26. Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren
    A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1276-1283 [Conf]
  27. Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia
    Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:221-226 [Conf]
  28. Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout
    A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:876-881 [Conf]
  29. Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    A SW performance estimation framework for early system-level-design using fine-grained instrumentation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:468-473 [Conf]
  30. Rainer Leupers
    Code Selection for Media Processors with SIMD Instructions. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:4-8 [Conf]
  31. Rainer Leupers
    Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:105-0 [Conf]
  32. Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, M. Pandey
    A design flow for configurable embedded processors based on optimized instruction set extension synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:581-586 [Conf]
  33. Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    An interprocedural code optimization technique for network processors using hardware multi-threading support. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:919-924 [Conf]
  34. Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
    RTL Processor Synthesis for Architecture Exploration and Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:156-160 [Conf]
  35. Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
    A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1256-1263 [Conf]
  36. Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Memory Access Micro-Profiling for ASIP Design. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:255-262 [Conf]
  37. Rainer Leupers, Peter Marwedel
    Algorithms for address assignment in DSP code generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:109-112 [Conf]
  38. Rainer Leupers, Peter Marwedel
    Function inlining under code size constraints for embedded processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:253-256 [Conf]
  39. Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis
    Low-Energy DSP Code Generation Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:431-437 [Conf]
  40. Rainer Leupers, Wolfgang Schenk, Peter Marwedel
    Microcode Generation for Flexible Parallel Target Architectures. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:247-256 [Conf]
  41. Rainer Leupers
    Code Generation for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:173-179 [Conf]
  42. Rainer Leupers
    HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:51-0 [Conf]
  43. Rainer Leupers, Fabian David
    A Uniform Optimization Technique for Offset Assignment Problems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:3-8 [Conf]
  44. Rainer Leupers, Peter Marwedel
    Time-constrained code compaction for DSPs. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:54-59 [Conf]
  45. Jens Wagner, Rainer Leupers
    C Compiler Design for an Industrial Network Processor. [Citation Graph (0, 0)][DBLP]
    LCTES/OM, 2001, pp:155-164 [Conf]
  46. Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr
    Application specific compiler/architecture codesign: a case study. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:185-193 [Conf]
  47. Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Integrated Verification Approach during ADL-Driven Processor Design. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:110-118 [Conf]
  48. Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    Optimization Techniques for ADL-Driven RTL Processor Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:165-171 [Conf]
  49. Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:138-148 [Conf]
  50. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:463-473 [Conf]
  51. Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Early ISS Integration into Network-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:443-452 [Conf]
  52. Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
    Improving Offset Assignment through Simultaneous Variable Coalescing. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:285-297 [Conf]
  53. Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:33-46 [Conf]
  54. Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie
    Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:167-181 [Conf]
  55. Anupam Basu, Rainer Leupers, Peter Marwedel
    Array Index Allocation under Register Constraints in DSP Programs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:330-335 [Conf]
  56. Rainer Leupers, Peter Marwedel
    Instruction-Set Modeling for ASIP Code Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:77-80 [Conf]
  57. Rainer Leupers
    Compiler Design Issues for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:51-58 [Journal]
  58. Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr
    Instruction Scheduler Generation for Retargetable Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:34-41 [Journal]
  59. Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
    A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1625-1639 [Journal]
  60. Jens Wagner, Rainer Leupers
    C compiler design for a network processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1302-1308 [Journal]
  61. Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
    Offset assignment using simultaneous variable coalescing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:4, pp:864-883 [Journal]
  62. Rainer Leupers, Steven Bashford
    Graph-based code selection techniques for embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:4, pp:794-814 [Journal]
  63. Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    A fast and generic hybrid simulation approach using C virtual machine. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:3-12 [Conf]
  64. Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1349-1354 [Conf]
  65. Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Design space exploration of partially re-configurable embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:319-324 [Conf]
  66. Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:189-194 [Conf]
  67. Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    ASIP architecture exploration for efficient IPSec encryption: A case study. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]
  68. Rainer Leupers, Peter Marwedel
    Time-constrained code compaction for DSPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:112-122 [Journal]
  69. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:235-246 [Journal]

  70. HySim: a fast simulation framework for embedded software development. [Citation Graph (, )][DBLP]


  71. A code-generator generator for multi-output instructions. [Citation Graph (, )][DBLP]


  72. A high-level virtual platform for early MPSoC software development. [Citation Graph (, )][DBLP]


  73. TotalProf: a fast and accurate retargetable source code profiler. [Citation Graph (, )][DBLP]


  74. MAPS: an integrated framework for MPSoC application parallelization. [Citation Graph (, )][DBLP]


  75. Multiprocessor performance estimation using hybrid simulation. [Citation Graph (, )][DBLP]


  76. Retargetable Code Optimization for Predicated Execution. [Citation Graph (, )][DBLP]


  77. System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. [Citation Graph (, )][DBLP]


  78. High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. [Citation Graph (, )][DBLP]


  79. Retargetable generation of code selectors from HDL processor models. [Citation Graph (, )][DBLP]


  80. Programming MPSoC platforms: Road works ahead! [Citation Graph (, )][DBLP]


  81. Cool MPSoC programming. [Citation Graph (, )][DBLP]


  82. Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. [Citation Graph (, )][DBLP]


  83. Instruction set extraction from programmable structures. [Citation Graph (, )][DBLP]


  84. Increasing data-bandwidth to instruction-set extensions through register clustering. [Citation Graph (, )][DBLP]


  85. Task management in MPSoCs: An ASIP approach. [Citation Graph (, )][DBLP]


  86. A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). [Citation Graph (, )][DBLP]


  87. A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. [Citation Graph (, )][DBLP]


  88. A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. [Citation Graph (, )][DBLP]


  89. A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding [Citation Graph (, )][DBLP]


Search in 0.108secs, Finished in 0.111secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002