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Jong Tae Kim:
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Publications of Author
- Jong Kang Park, Jong Tae Kim, Myung Chul Shin
High Performance Single Chip Implementation for a Digital Protective Relay Using FPGA. [Citation Graph (0, 0)][DBLP] ESA/VLSI, 2004, pp:504-508 [Conf]
- Chun-Guan Kim, Hongmoon Wang, Dae Jin Bae, Jong Tae Kim
VLSI Design of Multiple Specifications Viterbi Decoder. [Citation Graph (0, 0)][DBLP] ICWN, 2006, pp:497-502 [Conf]
- Keon-Myung Lee, Bong Ki Sohn, Jong Tae Kim, Seung Wook Lee, Ji Hyong Lee, Jae Wook Jeon, Jundong Cho
An SoC-Based Context-Aware System Architecture. [Citation Graph (0, 0)][DBLP] KES, 2004, pp:573-580 [Conf]
- Seung Wook Lee, Jong Tae Kim, Jae Sang Cha
Implementation of Adaptive Reed-Solomon Decoder for Context-Aware Mobile Computing Device. [Citation Graph (0, 0)][DBLP] KES (1), 2005, pp:1111-1117 [Conf]
- Seung Wook Lee, Jong Tae Kim, Bong Ki Sohn, Keon-Myung Lee, Jee-Hyung Lee, Jae Wook Jeon, Sukhan Lee
Real-Time System-on-a-Chip Architecture for Rule-Based Context-Aware Computing. [Citation Graph (0, 0)][DBLP] KES (1), 2005, pp:1014-1020 [Conf]
- Seung Wook Lee, Jong Tae Kim, Hongmoon Wang, Dae Jin Bae, Keon-Myung Lee, Jee-Hyung Lee, Jae Wook Jeon
Architecture of RETE Network Hardware Accelerator for Real-Time Context-Aware System. [Citation Graph (0, 0)][DBLP] KES (1), 2006, pp:401-408 [Conf]
- Jong Kang Park, Yong Ki Byun, Jong Tae Kim
Equivalent Electric Circuit Modeling of Differential Structures in PCB with Genetic Algorithm. [Citation Graph (0, 0)][DBLP] KES (3), 2006, pp:907-913 [Conf]
- Seok Min Yoon, Jong Tae Kim
Rule-Based Expert System for Designing DC-DC Converters. [Citation Graph (0, 0)][DBLP] KES (3), 2006, pp:914-921 [Conf]
- Seung Wook Lee, Jong Tae Kim
Universal Reed-Solomon Decoder Using Hardware/Software Co-Design Method. [Citation Graph (0, 0)][DBLP] VLSI, 2003, pp:279-284 [Conf]
- Seok Min Yoon, Seung Wook Lee, Hongmoon Wang, Jong Tae Kim
Encoding-Based Tamper-Resistant Algorithm for Mobile Device Security. [Citation Graph (0, 0)][DBLP] International Conference on Computational Science (4), 2007, pp:578-581 [Conf]
Pipeline Scheduling with Dual Voltages for Low Power Design. [Citation Graph (, )][DBLP]
Power Prediction of Application Software for Embedded System Based on PXA270 Processor. [Citation Graph (, )][DBLP]
Workload-Based Dynamic Voltage Scaling with the QoS for Streaming Video. [Citation Graph (, )][DBLP]
Radiation Pattern Reconstruction for Localization using Artificial Neural Network. [Citation Graph (, )][DBLP]
Memory Error Analysis in Temporal TMR Viterbi Decoder. [Citation Graph (, )][DBLP]
Hardware Accelerator Design for Crank Angle Sensor. [Citation Graph (, )][DBLP]
A soft error analysis tool for high-speed digital designs. [Citation Graph (, )][DBLP]
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