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Publications of Author

1. Avijit Dutta, Nur A. Touba
   Synthesis of Efficient Linear Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
   DFT, 2006, pp:206-214 [Conf]
   
2. Avijit Dutta, Terence Rodrigues, Nur A. Touba
   Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2005, pp:200-205 [Conf]
   
3. Avijit Dutta, Nur A. Touba
   Iterative OPDD Based Signal Probability Calculation. [Citation Graph (0, 0)][DBLP]
   VTS, 2006, pp:72-77 [Conf]
   
4. Avijit Dutta, Nur A. Touba
   Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. [Citation Graph (0, 0)][DBLP]
   VTS, 2007, pp:349-354 [Conf]
   
5. 
   Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. [Citation Graph (, )][DBLP]
   
   
6. 
   Partial Functional Manipulation Based Wirelength Minimization. [Citation Graph (, )][DBLP]
   
   
7. 
   Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. [Citation Graph (, )][DBLP]