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Ciaran Toal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ciaran Toal, Sakir Sezer
    A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA. [Citation Graph (0, 0)][DBLP]
    AICT/SAPIR/ELETE, 2005, pp:357-362 [Conf]
  2. Ciaran Toal, Sakir Sezer, Xing Yu
    A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:271-272 [Conf]
  3. Brendan McAllister, Sakir Sezer, Ciaran Toal
    Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1149-1152 [Conf]
  4. Emi Garcia-Palacios, Sakir Sezer, Ciaran Toal, Stephen Dawson
    Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access. [Citation Graph (0, 0)][DBLP]
    ICT, 2004, pp:876-884 [Conf]
  5. Ciaran Toal, Sakir Sezer
    The Implementation of Scalable ATM Frame Delineation Circuits. [Citation Graph (0, 0)][DBLP]
    ICT, 2004, pp:1047-1056 [Conf]
  6. Sakir Sezer, Ciaran Toal, Emi Garcia, V. Stewart
    A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  7. Ciaran Toal, Sakir Sezer
    A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:179- [Conf]
  8. Ciaran Toal, Sakir Sezer
    Investigation into programmability for layer 2 protocol frame delineation architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  9. Ciaran Toal, Sakir Sezer
    A 32-Bit SoPC Implementation of a P5. [Citation Graph (0, 0)][DBLP]
    ISCC, 2003, pp:504-507 [Conf]
  10. Ciaran Toal, Sakir Sezer, Xin Yang
    A VLSI GFP Frame Delineation Circuit. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:454-455 [Conf]

  11. An FPGA Based Memory Efficient Shared Buffer Implementation. [Citation Graph (, )][DBLP]


  12. An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing. [Citation Graph (, )][DBLP]


  13. FPGA-Based Lookup Circuit for Session-Based IP Packet Classification. [Citation Graph (, )][DBLP]


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