Conferences in DBLP
Steve Ferrera , Nicholas P. Carter Reconfigurable Circuits Using Hybrid Hall Effect Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Chao You , Jong-Ru Guo , Russell P. Kraft , Michael Chu , Robert W. Heikaus , Okan Erdogan , Peter F. Curran , Bryan S. Goda , Kuan Zhou , John F. McDonald Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Ebeling , Chris Fisher , Guanbin Xing , Manyuan Shen , Hui Liu Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Cardells-Tormo , Javier Valls-Coquillat , Vicenc Almenar-Terre Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Mohanty , Viktor K. Prasanna An Algorithm Designer's Workbench for Platform FPGA's. [Citation Graph (0, 0)][DBLP ] Conf ] Ludovico de Souza , Philip Ryan , Jason Crawford , Kevin Wong , Gregory B. Zyner , Tom McDermott Prototyping for the Concurrent Development. [Citation Graph (0, 0)][DBLP ] Conf ] Bingfeng Mei , Serge Vernalde , Diederik Verkest , Hugo De Man , Rudy Lauwereins ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. [Citation Graph (0, 0)][DBLP ] Conf ] Eryk Laskowski , Marek Tudruj Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Georgi Kuzmanov , Stamatis Vassiliadis Arbitrating Instructions in an pmu-Coded CCM. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas J. Wollinger , Christof Paar How Secure Are FPGAs in Cryptographic Applications? [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Luc Beuchat FPGA Implementations of the RC6 Block Cipher. [Citation Graph (0, 0)][DBLP ] Conf ] Máire McLoone , John V. McCanny Very High Speed 17 Gbps SHACAL Encryption Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine Compton , Scott Hauck Track Placement: Orchestrating Routing Structures to Maximize Routability. [Citation Graph (0, 0)][DBLP ] Conf ] Sean T. McCulloch , James P. Cohoon Quark Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge Barreiros , Ernesto Costa Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Enzler , Christian Plessl , Marco Platzner Virtualizing Hardware with Multi-context Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Akiya Jouraku , Kenichiro Anjo A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiro Kitaoka , Hideharu Amano , Kenichiro Anjo Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. [Citation Graph (0, 0)][DBLP ] Conf ] Gaël Rouvroy , François-Xavier Standaert , Jean-Jacques Quisquater , Jean-Didier Legat Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Gonzalez , Sergio López-Buedo , Francisco J. Gómez , Javier Martínez Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Allen Michalski , Kris Gaj , Tarek A. El-Ghazawi An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Michael G. Lorenz , Luis Mengibar , Luis Entrena , Raul Sánchez-Reillo Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Barat , Murali Jayapala , Tom Vander Aa , Rudy Lauwereins , Geert Deconinck , Henk Corporaal Low Power Coarse-Grained Reconfigurable Instruction Set Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Rohini Krishnan , José Pineda de Gyvez , Harry J. M. Veendrick Encoded-Low Swing Technique for Ultra Low Power Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Gareth Lee , George Milne Building Run-Time Reconfigurable Systems from Tiles. [Citation Graph (0, 0)][DBLP ] Conf ] Irwin Kennedy Exploiting Redundancy to Speedup Reconfiguration of an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Danne , Christophe Bobda , Heiko Kalte Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] François Charot , Eslam Yahya , Charles Wagner Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Giacinto Paolo Saggese , Antonino Mazzeo , Nicola Mazzocca , Antonio G. M. Strollo An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Nazar A. Saqib , Francisco Rodríguez-Henríquez , Arturo Díaz-Pérez Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core. [Citation Graph (0, 0)][DBLP ] Conf ] K. R. Shesha Shayee , Joonseok Park , Pedro C. Diniz Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Styles , Wayne Luk Branch Optimisation Techniques for Hardware Compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Jirong Liao , Weng-Fai Wong , Tulika Mitra A Model for Hardware Realization of Kernel Loops. [Citation Graph (0, 0)][DBLP ] Conf ] John Teifel , Rajit Manohar Programmable Asynchronous Pipeline Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Royal , Peter Y. K. Cheung Globally Asynchronous Locally Synchronous FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Van Court , Martin C. Herbordt , Richard J. Barton Case Study of a Functional Genomics Application. [Citation Graph (0, 0)][DBLP ] Conf ] C. W. Yu , K. H. Kwong , Kin-Hong Lee , Philip Heng Wai Leong A Smith-Waterman Systolic Cell. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Keller , Gordon J. Brebner , Philip James-Roxby Software Decelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Theerayod Wiangtong , Peter Y. K. Cheung , Wayne Luk A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Schmit Extra-dimensional Island-Style FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Stansfield Using Multiplexers for Control and Data in D-Fabrix. [Citation Graph (0, 0)][DBLP ] Conf ] Aneesh Koorapaty , Lawrence T. Pileggi , Herman Schmit Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Toshihito Fujiwara , Kenji Fujimoto , Tsutomu Maruyama A Real-Time Visualization System for PIV. [Citation Graph (0, 0)][DBLP ] Conf ] Yosuke Miyajima , Tsutomu Maruyama A Real-Time Stereo Vision System with FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Antonio Boluda , Fernando Pardo Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System. [Citation Graph (0, 0)][DBLP ] Conf ] Iouliia Skliarova , António de Brito Ferrari Reconfigurable Hardware SAT Solvers: A Survey of Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Feldmann , Christian Haubelt , Burkhard Monien , Jürgen Teich Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Roland H. C. Yap , Stella Z. Q. Wang , Martin Henz Hardware Implementations of Real-Time Reconfigurable WSAT Variants. [Citation Graph (0, 0)][DBLP ] Conf ] Unai Bidarte , Armando Astarloa , Aitzol Zuloaga , Jaime Jimenez , Iñigo Martínez de Alegría Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Seonil Choi , Viktor K. Prasanna Time and Energy Efficient Matrix Factorization Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] John Oliver , Venkatesh Akella Improving DSP Performance with a Small Amount of Field Programmable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Guillermo Payá Vayá , Marcos Martínez Peiró , Francisco Ballester , Francisco Mora Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Stavros Paschalakis , Peter Lee , Miroslaw Bober An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors. [Citation Graph (0, 0)][DBLP ] Conf ] Abdsamad Benkrid , Khaled Benkrid , Danny Crookes Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Brandon Blodget , Philip James-Roxby , Eric Keller , Scott McMillan , Prasanna Sundararajan A Self-reconfiguring Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Steiger , Herbert Walder , Marco Platzner Heuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Resano , Daniel Mozos , Diederik Verkest , Serge Vernalde , Francky Catthoor Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Théodore Marescaux , Jean-Yves Mignolet , Andrei Bartic , W. Moffat , Diederik Verkest , Serge Vernalde , Rudy Lauwereins Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] N. Pete Sedcole , Peter Y. K. Cheung , George A. Constantinides , Wayne Luk A Reconfigurable Platform for Real-Time Embedded Video Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Matteo Sonza Reorda , Massimo Violante Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. Çakir , Eike Grimpe , Wolfgang Nebel HW-Driven Emulation with Automatic Interface Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Lien Lu , Konrad Lai Implementation of HW$im - A Real-Time Configurable Cache Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Berube , Ashley Zinyk , José Nelson Amaral , Mike MacGregor The Bank Nth Chance Replacement Policy for FPGA-Based CAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Pasquale Corsonello , Stefania Perri , Maria Antonia Iachino , Giuseppe Cocorullo Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chang Hoon Kim , Soonhak Kwon , Jong Jin Kim , Chun Pyo Hong A New Arithmetic Unit in GF(2m ) for Reconfigurable Hardware Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Yann Thoma , Eduardo Sanchez , Juan-Manuel Moreno Arostegui , Gianluca Tempesti A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Leonel Sousa , Pedro Tomás , Francisco J. Pelayo , Antonio Martínez , Christian A. Morillas , Samuel F. Romero An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time. [Citation Graph (0, 0)][DBLP ] Conf ] François-Xavier Standaert , Loïc van Oldeneel tot Oldenzeel , David Samyde , Jean-Jacques Quisquater Power Analysis of FPGAs: How Practical is the Attack? [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Martina , Andrea Molino , Federico Quaglio , Fabrizio Vacca A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Benoit , Gilles Sassatelli , Lionel Torres , Michel Robert , Gaston Cambon , Didier Demigny A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Delvai , Ulrike Eisenmann , Wilfried Elmenreich A Generic Architecture for Integrated Smart Transducers. [Citation Graph (0, 0)][DBLP ] Conf ] Nuno Roma , Tiago Dias , Leonel Sousa Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoyoshi Kobori , Tsutomu Maruyama A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Osana , Tomonori Fukushima , Hideharu Amano Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Joaquín Cerdá , Rafael Gadea Gironés , Vicente Herrero , Angel Sebastia On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Daly , William P. Marnane , Tim Kerins , Emanuel M. Popovici Fast Modular Division for Application in ECC on Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-U Lee , Wayne Luk , John D. Villasenor , Peter Y. K. Cheung Non-uniform Segmentation for Hardware Function Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Barry Lee , Neil Burgess A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] J. Soares Augusto , Carlos Beltrán Almeida , H. C. Campos Neto A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] A. Parreira , João Paulo Teixeira , A. Pantelimon , Marcelino B. Santos , José T. de Sousa Fault Simulation Using Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Seyed Ghassem Miremadi , Ali Reza Ejlali Switch Level Fault Emulation. [Citation Graph (0, 0)][DBLP ] Conf ] John W. Lockwood , Christopher E. Neely , Christopher K. Zuver , James Moscola , Sarang Dharmapurikar , David Lim An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Bellows , Jaroslav Flidr , Ladan Gharai , Colin Perkins , Pawel Chodowiec , Kris Gaj IPsec-Protected Transport of HDTV over IP. [Citation Graph (0, 0)][DBLP ] Conf ] Ioannis Sourdis , Dionisios N. Pnevmatikatos Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System. [Citation Graph (0, 0)][DBLP ] Conf ] T. K. Lee , Sherif Yusuf , Wayne Luk , Morris Sloman , Emil Lupu , Naranker Dulay Irregular Reconfigurable CAM Structures for Firewall Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Moscu Panainte , Koen Bertels , Stamatis Vassiliadis Compiling for the Molen Programming Paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Claudiu Zissulescu , Todor Stefanov , Bart Kienhuis , Ed F. Deprettere Laura: Leiden Architecture Research and Exploration Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Lilian Bossuet , Guy Gogniat , Jean Luc Philippe Communication Costs Driven Design Space Exploration for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Linda Kaouane , Mohamed Akil , Yves Sorel , Thierry Grandpierre From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Stuart Colsell , Reuben Edwards Adaptive Real-Time Systems and the FPAA. [Citation Graph (0, 0)][DBLP ] Conf ] Mark E. Dunham , Michael P. Caffrey , Paul S. Graham Challenges and Successes in Space Based Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeyuki Takano Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher R. Clark , David E. Schimmel Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Roland Höller FPGAs for High Accuracy Clock Synchronization over Ethernet Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jiri Novotný , Otto Fucík , David Antos Project of IPv6 Router with FPGA Hardware Accelerator. [Citation Graph (0, 0)][DBLP ] Conf ] David V. Schuehler , Harvey Ku , John W. Lockwood A TCP/IP Based Multi-device Programming Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Turner , Roger Woods Design Flow for Efficient FPGA Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Sklyarov , Iouliia Skliarova , Pedro Almeida , Manuel Almeida High-Level Design Tools for FPGA-Based Combinatorial Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Denning , Neil Harold , Malachy Devlin , James Irvine Using System Generator to Design a Reconfigurable Video Encryption System. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav Lícko , Jan Schier , Milan Tichý , Markus Kühl MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping. [Citation Graph (0, 0)][DBLP ] Conf ] J. Marí-Roig , V. Torres , Ma José Canet , A. Pérez , T. Sansaloni , Francisco Cardells-Tormo , F. Angarita , Felip Vicedo , Vicenc Almenar-Terre , Javier Valls-Coquillat DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Nestor FPGA Implementation of a Maze Routing Accelerator. [Citation Graph (0, 0)][DBLP ] Conf ] John Cochran , Deepak Kapur , Darko Stefanovic Model Checking Reconfigurable Processor Configurations for Safety Properties. [Citation Graph (0, 0)][DBLP ] Conf ] Renqiu Huang , Tommy Cheung , Ted Kok A Statistical Analysis Tool for FPLD Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Velten , Anton Kummert FPGA-Implementation of Signal Processing Algorithms for Video Based Industrial Safety Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Cesar Torres-Huitzil , Miguel Arias-Estrada Configurable Hardware Architecture for Real-Time Window-Based Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled Benkrid , S. Sukhsawas , Danny Crookes , Abdsamad Benkrid An FPGA-Based Image Connected Component Labeller. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Gadea Gironés , Agustín Ramirez-Agundis , Joaquín Cerdá-Boluda , Ricardo José Colom-Palero FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Sklyarov , Iouliia Skliarova Reconfigurable Systems in Education. [Citation Graph (0, 0)][DBLP ] Conf ] Shoji Yamamoto , Shuichi Ichikawa , Hiroshi Yamamoto Data Dependent Circuit Design: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Martina , Andrea Molino , Mario Nicola , Fabrizio Vacca Design of a Power Conscious, Customizable CDMA Receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Konstantinos Tatas , K. Siozios , Dimitrios Soudris , Adonios Thanailakis Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Pilar Martínez Ortigosa , O. López , R. Estrada , Inmaculada García , Ester M. Garzón A VHDL Library to Analyse Fault Tolerant Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Per Haglund , Oskar Mencer , Wayne Luk , Benjamin Tai Hardware Design with a Scripting Language. [Citation Graph (0, 0)][DBLP ] Conf ] L. Kalyan Kumar , Amol J. Mupid , Aditya S. Ramani , V. Kamakoti Testable Clock Routing Architecture for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Eva M. Ortigosa , Pilar Martínez Ortigosa , Antonio Cañas , Eduardo Ros , Rodrigo Agís , Julio Ortega FPGA Implemenation of Multi-layer Perceptrons for Speech Recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Juan M. Xicotencatl , Miguel Arias-Estrada FPGA Based High Density Spiking Neural Network Array. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Jiang , Wayne Luk , Daniel Rueckert FPGA-Based Computation of Free-Form Deformations. [Citation Graph (0, 0)][DBLP ] Conf ] Jihan Zhu , Peter Sutton FPGA Implementations of Neural Networks - A Survey of a Decade of Progress. [Citation Graph (0, 0)][DBLP ] Conf ] Aurel Netin , Dumitru Roman , Octavian Cret , Kalman Pusztai , Lucia Vacariu FPGA-Based Hardware/Software CoDesign of an Expert System Shell. [Citation Graph (0, 0)][DBLP ] Conf ] Theerayod Wiangtong , Peter Y. K. Cheung , Wayne Luk Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Simka , Viktor Fischer , Milos Drutarovský Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Harkin , Michael Callaghan , Chris Peters , T. Martin McGinnity , Liam P. Maguire On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Schmidt , Andreas Koch Fast Region Labeling on the Reconfigurable Platform ACE-V. [Citation Graph (0, 0)][DBLP ] Conf ] Jesús Lázaro , Jagoba Arias , José Luis Martín , Carlos Cuadrado Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications. [Citation Graph (0, 0)][DBLP ] Conf ] David Rodríguez Lozano , Juan Manuel Sánchez-Pérez , Juan Antonio Gómez Pulido Reconfigurable Hybrid Architecture for Web Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Antonin Hermanek , Zdenek Pohl , Jiri Kadlec FPGA Implementation of the Adpaptive Lattice Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Ballagh , James Hwang , H. Ma , Brent Milne , Nabeel Shirazi , Vinay Singh , Jeffrey D. Stroomer Specifying Control Logic for DSP Applications in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Selene Maya-Rueda , Miguel Arias-Estrada FPGA Processor for Real-Time Optical Flow Computation. [Citation Graph (0, 0)][DBLP ] Conf ] María Dolores Valdés , María José Moure , Camilo Quintáns , Enrique Mandado A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Murgan , Mihail Petrov , Alberto García Ortiz , Ralf Ludewig , Peter Zipf , Thomas Hollstein , Manfred Glesner , Bernard Ölkrug , Jörg Brakensiek Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Dylan Carline , Paul Coulton A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Sergej Sawitzki , Rainer G. Spallek Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Bobda , Klaus Danne , André Linarth Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Imaña , Juan Manuel Sánchez A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2m ). [Citation Graph (0, 0)][DBLP ] Conf ] Fernando E. Ortiz , John R. Humphrey , James P. Durbano , Dennis W. Prather A Study on the Design of Floating-Point Functions in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Ramírez , Uwe Meyer-Bäse , Antonio García , Antonio Lloris-Ruíz Design and Implementation of RNS-Based Adaptive Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Sami Khawam , Tughrul Arslan , Fred Westall Domain-Specific Reconfigurable Array for Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoya Kitani , Yoshifumi Takamoto , Isao Naka , Keiichi Yasumoto , Akio Nakata , Teruo Higashino Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Brendan McAllister , Sakir Sezer , Ciaran Toal Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. [Citation Graph (0, 0)][DBLP ] Conf ] Shaomeng Li , Jim Torresen , Oddvar Søråsen Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Vanderlei Bonato , Rolf Fredi Molz , João Carlos Furtado , Marcos Flôres Ferrão , Fernando Gehm Moraes Propose of a Hardware Implementation for Fingerprint Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Damian Dalton , Vivian Bessler , Jeffrey Griffiths , Andrew McCarthy , Abhay Vadher , Rory O'Kane , Rob Quigley , Declan O'Connor APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Vinu Vijay Kumar , John Lach Designing, Scheduling, and Allocating Flexible Arithmetic Components. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Angel Aguirre Echánove , Jonathan Noel Tombs , Antonio Jesús Torralba Silgado , Leopoldo García Franquelo UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging. [Citation Graph (0, 0)][DBLP ] Conf ] 