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Conferences in DBLP

Field-Programmable Logic and Applications (FPL) (fpl)
2003 (conf/fpl/2003)

  1. Steve Ferrera, Nicholas P. Carter
    Reconfigurable Circuits Using Hybrid Hall Effect Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1-10 [Conf]
  2. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert W. Heikaus, Okan Erdogan, Peter F. Curran, Bryan S. Goda, Kuan Zhou, John F. McDonald
    Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:11-20 [Conf]
  3. Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu
    Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:21-30 [Conf]
  4. Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre
    Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:31-40 [Conf]
  5. Sumit Mohanty, Viktor K. Prasanna
    An Algorithm Designer's Workbench for Platform FPGA's. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:41-50 [Conf]
  6. Ludovico de Souza, Philip Ryan, Jason Crawford, Kevin Wong, Gregory B. Zyner, Tom McDermott
    Prototyping for the Concurrent Development. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:51-60 [Conf]
  7. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
    ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:61-70 [Conf]
  8. Eryk Laskowski, Marek Tudruj
    Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:71-80 [Conf]
  9. Georgi Kuzmanov, Stamatis Vassiliadis
    Arbitrating Instructions in an pmu-Coded CCM. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:81-90 [Conf]
  10. Thomas J. Wollinger, Christof Paar
    How Secure Are FPGAs in Cryptographic Applications? [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:91-100 [Conf]
  11. Jean-Luc Beuchat
    FPGA Implementations of the RC6 Block Cipher. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:101-110 [Conf]
  12. Máire McLoone, John V. McCanny
    Very High Speed 17 Gbps SHACAL Encryption Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:111-120 [Conf]
  13. Katherine Compton, Scott Hauck
    Track Placement: Orchestrating Routing Structures to Maximize Routability. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:121-130 [Conf]
  14. Sean T. McCulloch, James P. Cohoon
    Quark Routing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:131-140 [Conf]
  15. Jorge Barreiros, Ernesto Costa
    Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:141-150 [Conf]
  16. Rolf Enzler, Christian Plessl, Marco Platzner
    Virtualizing Hardware with Multi-context Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:151-160 [Conf]
  17. Hideharu Amano, Akiya Jouraku, Kenichiro Anjo
    A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:161-170 [Conf]
  18. Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo
    Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:171-180 [Conf]
  19. Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:181-193 [Conf]
  20. Ivan Gonzalez, Sergio López-Buedo, Francisco J. Gómez, Javier Martínez
    Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:194-203 [Conf]
  21. Allen Michalski, Kris Gaj, Tarek A. El-Ghazawi
    An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:204-219 [Conf]
  22. Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo
    Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:220-229 [Conf]
  23. Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal
    Low Power Coarse-Grained Reconfigurable Instruction Set Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:230-239 [Conf]
  24. Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick
    Encoded-Low Swing Technique for Ultra Low Power Interconnect. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:240-251 [Conf]
  25. Gareth Lee, George Milne
    Building Run-Time Reconfigurable Systems from Tiles. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:252-261 [Conf]
  26. Irwin Kennedy
    Exploiting Redundancy to Speedup Reconfiguration of an FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:262-271 [Conf]
  27. Klaus Danne, Christophe Bobda, Heiko Kalte
    Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:272-281 [Conf]
  28. François Charot, Eslam Yahya, Charles Wagner
    Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:282-291 [Conf]
  29. Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo
    An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:292-302 [Conf]
  30. Nazar A. Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez
    Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:303-312 [Conf]
  31. K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz
    Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:313-323 [Conf]
  32. Henry Styles, Wayne Luk
    Branch Optimisation Techniques for Hardware Compilation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:324-333 [Conf]
  33. Jirong Liao, Weng-Fai Wong, Tulika Mitra
    A Model for Hardware Realization of Kernel Loops. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:334-344 [Conf]
  34. John Teifel, Rajit Manohar
    Programmable Asynchronous Pipeline Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:345-354 [Conf]
  35. Andrew Royal, Peter Y. K. Cheung
    Globally Asynchronous Locally Synchronous FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:355-364 [Conf]
  36. Tom Van Court, Martin C. Herbordt, Richard J. Barton
    Case Study of a Functional Genomics Application. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:365-374 [Conf]
  37. C. W. Yu, K. H. Kwong, Kin-Hong Lee, Philip Heng Wai Leong
    A Smith-Waterman Systolic Cell. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:375-384 [Conf]
  38. Eric Keller, Gordon J. Brebner, Philip James-Roxby
    Software Decelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:385-395 [Conf]
  39. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:396-405 [Conf]
  40. Herman Schmit
    Extra-dimensional Island-Style FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:406-415 [Conf]
  41. Tony Stansfield
    Using Multiplexers for Control and Data in D-Fabrix. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:416-425 [Conf]
  42. Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit
    Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:426-436 [Conf]
  43. Toshihito Fujiwara, Kenji Fujimoto, Tsutomu Maruyama
    A Real-Time Visualization System for PIV. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:437-447 [Conf]
  44. Yosuke Miyajima, Tsutomu Maruyama
    A Real-Time Stereo Vision System with FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:448-457 [Conf]
  45. Jose Antonio Boluda, Fernando Pardo
    Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:458-467 [Conf]
  46. Iouliia Skliarova, António de Brito Ferrari
    Reconfigurable Hardware SAT Solvers: A Survey of Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:468-477 [Conf]
  47. Rainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen Teich
    Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:478-487 [Conf]
  48. Roland H. C. Yap, Stella Z. Q. Wang, Martin Henz
    Hardware Implementations of Real-Time Reconfigurable WSAT Variants. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:488-496 [Conf]
  49. Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría
    Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:497-506 [Conf]
  50. Seonil Choi, Viktor K. Prasanna
    Time and Energy Efficient Matrix Factorization Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:507-519 [Conf]
  51. John Oliver, Venkatesh Akella
    Improving DSP Performance with a Small Amount of Field Programmable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:520-532 [Conf]
  52. Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco Ballester, Francisco Mora
    Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:533-542 [Conf]
  53. Stavros Paschalakis, Peter Lee, Miroslaw Bober
    An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:543-552 [Conf]
  54. Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
    Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:553-564 [Conf]
  55. Brandon Blodget, Philip James-Roxby, Eric Keller, Scott McMillan, Prasanna Sundararajan
    A Self-reconfiguring Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:565-574 [Conf]
  56. Christoph Steiger, Herbert Walder, Marco Platzner
    Heuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:575-584 [Conf]
  57. Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor
    Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:585-594 [Conf]
  58. Théodore Marescaux, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
    Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:595-605 [Conf]
  59. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Reconfigurable Platform for Real-Time Embedded Video Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:606-615 [Conf]
  60. Matteo Sonza Reorda, Massimo Violante
    Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:616-626 [Conf]
  61. M. Çakir, Eike Grimpe, Wolfgang Nebel
    HW-Driven Emulation with Automatic Interface Generation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:627-637 [Conf]
  62. Shih-Lien Lu, Konrad Lai
    Implementation of HW$im - A Real-Time Configurable Cache Simulator. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:638-647 [Conf]
  63. Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike MacGregor
    The Bank Nth Chance Replacement Policy for FPGA-Based CAMs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:648-660 [Conf]
  64. Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo
    Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:661-669 [Conf]
  65. Chang Hoon Kim, Soonhak Kwon, Jong Jin Kim, Chun Pyo Hong
    A New Arithmetic Unit in GF(2m) for Reconfigurable Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:670-680 [Conf]
  66. Yann Thoma, Eduardo Sanchez, Juan-Manuel Moreno Arostegui, Gianluca Tempesti
    A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:681-690 [Conf]
  67. Leonel Sousa, Pedro Tomás, Francisco J. Pelayo, Antonio Martínez, Christian A. Morillas, Samuel F. Romero
    An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:691-700 [Conf]
  68. François-Xavier Standaert, Loïc van Oldeneel tot Oldenzeel, David Samyde, Jean-Jacques Quisquater
    Power Analysis of FPGAs: How Practical is the Attack? [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:701-711 [Conf]
  69. Maurizio Martina, Andrea Molino, Federico Quaglio, Fabrizio Vacca
    A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:712-721 [Conf]
  70. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny
    A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:722-732 [Conf]
  71. Martin Delvai, Ulrike Eisenmann, Wilfried Elmenreich
    A Generic Architecture for Integrated Smart Transducers. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:733-744 [Conf]
  72. Nuno Roma, Tiago Dias, Leonel Sousa
    Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:745-754 [Conf]
  73. Tomoyoshi Kobori, Tsutomu Maruyama
    A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:755-765 [Conf]
  74. Yasunori Osana, Tomonori Fukushima, Hideharu Amano
    Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:766-775 [Conf]
  75. Joaquín Cerdá, Rafael Gadea Gironés, Vicente Herrero, Angel Sebastia
    On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:776-785 [Conf]
  76. Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici
    Fast Modular Division for Application in ECC on Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:786-795 [Conf]
  77. Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
    Non-uniform Segmentation for Hardware Function Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:796-807 [Conf]
  78. Barry Lee, Neil Burgess
    A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:808-817 [Conf]
  79. J. Soares Augusto, Carlos Beltrán Almeida, H. C. Campos Neto
    A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:818-827 [Conf]
  80. Andrzej Krasniewski
    Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:828-838 [Conf]
  81. A. Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa
    Fault Simulation Using Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:839-848 [Conf]
  82. Seyed Ghassem Miremadi, Ali Reza Ejlali
    Switch Level Fault Emulation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:849-858 [Conf]
  83. John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David Lim
    An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:859-868 [Conf]
  84. Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj
    IPsec-Protected Transport of HDTV over IP. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:869-879 [Conf]
  85. Ioannis Sourdis, Dionisios N. Pnevmatikatos
    Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:880-889 [Conf]
  86. T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay
    Irregular Reconfigurable CAM Structures for Firewall Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:890-899 [Conf]
  87. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Compiling for the Molen Programming Paradigm. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:900-910 [Conf]
  88. Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. Deprettere
    Laura: Leiden Architecture Research and Exploration Tool. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:911-920 [Conf]
  89. Lilian Bossuet, Guy Gogniat, Jean Luc Philippe
    Communication Costs Driven Design Space Exploration for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:921-933 [Conf]
  90. Linda Kaouane, Mohamed Akil, Yves Sorel, Thierry Grandpierre
    From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:934-943 [Conf]
  91. Stuart Colsell, Reuben Edwards
    Adaptive Real-Time Systems and the FPAA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:944-947 [Conf]
  92. Mark E. Dunham, Michael P. Caffrey, Paul S. Graham
    Challenges and Successes in Space Based Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:948-951 [Conf]
  93. Shigeyuki Takano
    Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:952-955 [Conf]
  94. Christopher R. Clark, David E. Schimmel
    Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:956-959 [Conf]
  95. Roland Höller
    FPGAs for High Accuracy Clock Synchronization over Ethernet Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:960-963 [Conf]
  96. Jiri Novotný, Otto Fucík, David Antos
    Project of IPv6 Router with FPGA Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:964-967 [Conf]
  97. David V. Schuehler, Harvey Ku, John W. Lockwood
    A TCP/IP Based Multi-device Programming Circuit. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:968-971 [Conf]
  98. Richard H. Turner, Roger Woods
    Design Flow for Efficient FPGA Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:972-975 [Conf]
  99. Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida
    High-Level Design Tools for FPGA-Based Combinatorial Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:976-979 [Conf]
  100. Daniel Denning, Neil Harold, Malachy Devlin, James Irvine
    Using System Generator to Design a Reconfigurable Video Encryption System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:980-983 [Conf]
  101. Miroslav Lícko, Jan Schier, Milan Tichý, Markus Kühl
    MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:984-987 [Conf]
  102. J. Marí-Roig, V. Torres, Ma José Canet, A. Pérez, T. Sansaloni, Francisco Cardells-Tormo, F. Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat
    DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:988-991 [Conf]
  103. John A. Nestor
    FPGA Implementation of a Maze Routing Accelerator. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:992-995 [Conf]
  104. John Cochran, Deepak Kapur, Darko Stefanovic
    Model Checking Reconfigurable Processor Configurations for Safety Properties. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:996-999 [Conf]
  105. Renqiu Huang, Tommy Cheung, Ted Kok
    A Statistical Analysis Tool for FPLD Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1000-1003 [Conf]
  106. Jörg Velten, Anton Kummert
    FPGA-Implementation of Signal Processing Algorithms for Video Based Industrial Safety Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1004-1007 [Conf]
  107. Cesar Torres-Huitzil, Miguel Arias-Estrada
    Configurable Hardware Architecture for Real-Time Window-Based Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1008-1011 [Conf]
  108. Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid
    An FPGA-Based Image Connected Component Labeller. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1012-1015 [Conf]
  109. Rafael Gadea Gironés, Agustín Ramirez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero
    FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1016-1019 [Conf]
  110. Valery Sklyarov, Iouliia Skliarova
    Reconfigurable Systems in Education. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1020-1023 [Conf]
  111. Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto
    Data Dependent Circuit Design: A Case Study. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1024-1027 [Conf]
  112. Maurizio Martina, Andrea Molino, Mario Nicola, Fabrizio Vacca
    Design of a Power Conscious, Customizable CDMA Receiver. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1028-1031 [Conf]
  113. Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis
    Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1032-1035 [Conf]
  114. Pilar Martínez Ortigosa, O. López, R. Estrada, Inmaculada García, Ester M. Garzón
    A VHDL Library to Analyse Fault Tolerant Techniques. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1036-1039 [Conf]
  115. Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai
    Hardware Design with a Scripting Language. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1040-1043 [Conf]
  116. L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
    Testable Clock Routing Architecture for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1044-1047 [Conf]
  117. Eva M. Ortigosa, Pilar Martínez Ortigosa, Antonio Cañas, Eduardo Ros, Rodrigo Agís, Julio Ortega
    FPGA Implemenation of Multi-layer Perceptrons for Speech Recognition. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1048-1052 [Conf]
  118. Juan M. Xicotencatl, Miguel Arias-Estrada
    FPGA Based High Density Spiking Neural Network Array. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1053-1056 [Conf]
  119. Jun Jiang, Wayne Luk, Daniel Rueckert
    FPGA-Based Computation of Free-Form Deformations. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1057-1061 [Conf]
  120. Jihan Zhu, Peter Sutton
    FPGA Implementations of Neural Networks - A Survey of a Decade of Progress. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1062-1066 [Conf]
  121. Aurel Netin, Dumitru Roman, Octavian Cret, Kalman Pusztai, Lucia Vacariu
    FPGA-Based Hardware/Software CoDesign of an Expert System Shell. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1067-1070 [Conf]
  122. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
    Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1071-1074 [Conf]
  123. Martin Simka, Viktor Fischer, Milos Drutarovský
    Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1075-1078 [Conf]
  124. Jim Harkin, Michael Callaghan, Chris Peters, T. Martin McGinnity, Liam P. Maguire
    On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1079-1082 [Conf]
  125. Christian Schmidt, Andreas Koch
    Fast Region Labeling on the Reconfigurable Platform ACE-V. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1083-1086 [Conf]
  126. Jesús Lázaro, Jagoba Arias, José Luis Martín, Carlos Cuadrado
    Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1087-1090 [Conf]
  127. David Rodríguez Lozano, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido
    Reconfigurable Hybrid Architecture for Web Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1091-1094 [Conf]
  128. Antonin Hermanek, Zdenek Pohl, Jiri Kadlec
    FPGA Implementation of the Adpaptive Lattice Filter. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1095-1098 [Conf]
  129. Jonathan Ballagh, James Hwang, H. Ma, Brent Milne, Nabeel Shirazi, Vinay Singh, Jeffrey D. Stroomer
    Specifying Control Logic for DSP Applications in FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1099-1102 [Conf]
  130. Selene Maya-Rueda, Miguel Arias-Estrada
    FPGA Processor for Real-Time Optical Flow Computation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1103-1106 [Conf]
  131. María Dolores Valdés, María José Moure, Camilo Quintáns, Enrique Mandado
    A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1107-1110 [Conf]
  132. Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
    Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1111-1114 [Conf]
  133. Dylan Carline, Paul Coulton
    A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1115-1118 [Conf]
  134. Sergej Sawitzki, Rainer G. Spallek
    Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1119-1122 [Conf]
  135. Christophe Bobda, Klaus Danne, André Linarth
    Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1123-1126 [Conf]
  136. José Luis Imaña, Juan Manuel Sánchez
    A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2m). [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1127-1130 [Conf]
  137. Fernando E. Ortiz, John R. Humphrey, James P. Durbano, Dennis W. Prather
    A Study on the Design of Floating-Point Functions in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1131-1134 [Conf]
  138. Javier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz
    Design and Implementation of RNS-Based Adaptive Filters. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1135-1138 [Conf]
  139. Sami Khawam, Tughrul Arslan, Fred Westall
    Domain-Specific Reconfigurable Array for Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1139-1144 [Conf]
  140. Tomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
    Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1145-1148 [Conf]
  141. Brendan McAllister, Sakir Sezer, Ciaran Toal
    Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1149-1152 [Conf]
  142. Shaomeng Li, Jim Torresen, Oddvar Søråsen
    Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1153-1157 [Conf]
  143. Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes
    Propose of a Hardware Implementation for Fingerprint Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1158-1161 [Conf]
  144. Damian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O'Kane, Rob Quigley, Declan O'Connor
    APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1162-1165 [Conf]
  145. Vinu Vijay Kumar, John Lach
    Designing, Scheduling, and Allocating Flexible Arithmetic Components. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1166-1169 [Conf]
  146. Miguel Angel Aguirre Echánove, Jonathan Noel Tombs, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo
    UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1170-1173 [Conf]
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