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Yarsun Hsu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sheng-Kai Hung, Yarsun Hsu
    Modularized Redundant Parallel Virtual File System. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:186-199 [Conf]
  2. Sheng-Kai Hung, Yarsun Hsu
    Striping Cache: A Global Cache for Striped Network File System. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:387-393 [Conf]
  3. Sang Lyul Min, Yarsun Hsu, Hyoung-Joo Kim
    A Design of Performance-optimized Control-based Synchronization. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1990, pp:312-323 [Conf]
  4. Sheng-Kai Hung, Yarsun Hsu
    DPCT: Distributed Parity Cache Table for Redundant Parallel File System. [Citation Graph (0, 0)][DBLP]
    HPCC, 2006, pp:320-329 [Conf]
  5. Jesse Fang, Yarsun Hsu, Shing-Tsaan Huang, Jie-Yong Juang, W. H. Tsai, Horst Wedde
    Are We Providing the Right Education for Computer Science/Engineering Students? [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:14-15 [Conf]
  6. Yarsun Hsu
    Parallel Systems and Parallel I/O Technology. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:4- [Conf]
  7. Sandra Johnson Baylor, Yarsun Hsu
    The Effects of Network Delays on the Performance of MIN-Based Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:292-295 [Conf]
  8. Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu
    Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:163-170 [Conf]
  9. Sandra Johnson Baylor, Caroline Benveniste, Yarsun Hsu
    Performance Evaluation of a Parallel I/O Architecture. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:404-413 [Conf]
  10. Ching-Farn Eric Wu, Yew-Huey Liu, Yarsun Hsu
    Timestamp consistency and trace-driven analysis for distributed parallel systems. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:680-0 [Conf]
  11. Jin-Soo Kim, Yarsun Hsu
    Memory system behavior of Java programs: methodology and analysis. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2000, pp:264-274 [Conf]
  12. Peter F. Corbett, Dror G. Feitelson, Jean-Pierre Prost, George S. Almasi, Sandra Johnson Baylor, Anthony Bolmarcich, Yarsun Hsu, Julian Satran, Marc Snir, Robert Colao, Brian D. Herr, Joe Kavaky, Thomas R. Morgan, Anthony Zlotek
    Parallel File Systems for the IBM SP Computers. [Citation Graph (0, 0)][DBLP]
    IBM Systems Journal, 1995, v:34, n:2, pp:222-248 [Journal]
  13. Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu
    A Quantitative Evaluation of Cache Types for High-Performance Computer Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:10, pp:1154-1162 [Journal]
  14. Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu
    Efficient Stack Simulation for Set-Associative Virtual Address Cache with Real Tags. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:719-723 [Journal]
  15. Po-Chun Liu, Sheng-Kai Hung, Yarsun Hsu
    Security Enhancement and Performance Evaluation of an Object-Based Storage System. [Citation Graph (0, 0)][DBLP]
    HPCC, 2007, pp:408-419 [Conf]
  16. Lungpin Yeh, Juei-Ting Sun, Sheng-Kai Hung, Yarsun Hsu
    A Windows-Based Parallel File System. [Citation Graph (0, 0)][DBLP]
    HPCC, 2007, pp:7-18 [Conf]
  17. Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yar-Sun Hsu
    A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2754-2757 [Conf]

  18. Cycle Stealing and Channel Management for On-Chip Networks. [Citation Graph (, )][DBLP]

  19. A Flexible and Cost-Effective File-Wise Reliability Scheme for Storage Systems. [Citation Graph (, )][DBLP]

  20. Emulation of Object-Based Storage Devices by a Virtual Machine. [Citation Graph (, )][DBLP]

  21. A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. [Citation Graph (, )][DBLP]

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