The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Radu Muresan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Radu Muresan, Catherine H. Gebotys
    Current flattening in software and hardware for security applications. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:218-223 [Conf]
  2. Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano Gregori
    Power-smart system-on-chip architecture for embedded cryptosystems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:184-189 [Conf]
  3. Catherine H. Gebotys, Radu Muresan
    Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:205-216 [Conf]
  4. Xuequn Li, Haleh Vahedi, Radu Muresan, Stefano Gregori
    An integrated current flattening module for embedded cryptosystems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:436-439 [Conf]
  5. Radu Muresan, Catherine H. Gebotys
    Current consumption dynamics at instruction and program level for a VLIW DSP processor. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:130-135 [Conf]
  6. Radu Muresan, Catherine H. Gebotys
    Instantaneous current modeling in a complex VLIW processor core. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:415-451 [Journal]
  7. Haleh Vahedi, Radu Muresan, Stefano Gregori
    On-chip current flattening circuit with dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002