Conferences in DBLP

IFIP WG10.5 (ifip10-5)
2001 (conf/ifip10-5/2001)

1. P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, M. Karabernou
   Two ASIC for Low and Middle Levels of Real Time Image Processing. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:3-14 [Conf]
   
2. Takashi Komuro, Masatoshi Ishikawa
   64×64 Pixels General Purpose Digital Vision Chip. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:15-26 [Conf]
   
3. Eric Senn, Eric Martin
   A Vision System on Chip for Industrial Control. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:27-38 [Conf]
   
4. Didier Demigny, Lounis Kessal, J. Pons
   Fast Recursive Implementation of the Gaussian Filter. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:39-49 [Conf]
   
5. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
   A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:51-62 [Conf]
   
6. Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy
   Dynamically Reconfigurable Architectures for Digital Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:63-74 [Conf]
   
7. Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, M. Karabernou
   Reconfigurable Architecture Using High Speed FPGA. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:75-86 [Conf]
   
8. Raul Camposano, Don MacMillen
   Design Technology for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:87-96 [Conf]
   
9. Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis
   Distributed Collaborative Design over Cave2 Framework. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:97-108 [Conf]
   
10. Morgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa
    High Performance Java Hardware Engine and Software Kernel for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:109-120 [Conf]
    
11. João Cláudio Soares Otero, Flávio Rech Wagner
    An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:121-132 [Conf]
    
12. David Bernard, Christian Landrault, Pascal Nouet
    Interconnect Capacitance Modelling in a VDSM CMOS Technology. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:133-144 [Conf]
    
13. C. Araujo, Edna Barros
    Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:145-156 [Conf]
    
14. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:157-168 [Conf]
    
15. Amaury Nève, Denis Flandre
    Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:169-180 [Conf]
    
16. Braulio Adriano de Mello, Flávio Rech Wagner
    A Standardized Co-simulation Backbone. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:181-192 [Conf]
    
17. Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya
    Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:193-204 [Conf]
    
18. Catherine H. Gebotys, Radu Muresan
    Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:205-216 [Conf]
    
19. Patricia Guitton-Ouhamou, Cécile Belleudy, Michel Auguin
    Power Consumption Model for the DSP OAK Processor. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:217-228 [Conf]
    
20. J. M. Dutertre, F. M. Roche, Guy Cathebras
    Integration of Robustness in the Design of a Cell. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:229-239 [Conf]
    
21. Vincent Beroulle, Laurent Latorre, M. Dardalhon, C. Oudea, G. Perez, F. Pressecq, Pascal Nouet
    Impact of Technology Spreading on MEMS design Robustness. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:241-251 [Conf]
    
22. Nuno Roma, Leonel Sousa
    A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:253-264 [Conf]
    
23. Stephen M. Pisuk, Peter H. Wu
    Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:265-276 [Conf]
    
24. Kiyoo Itoh, Hiroyuki Mizuno
    Low-Voltage Embedded-RAM Technology: Present and Future. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:277-288 [Conf]
    
25. Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi
    Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:289-300 [Conf]
    
26. Philippe Maurine, Nadine Azémard, Daniel Auvergne
    Gate Sizing for Low Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:301-312 [Conf]
    
27. Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin
    Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:313-324 [Conf]
    
28. Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne
    Feasible Delay Bound Definition. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:325-335 [Conf]
    
29. Jung Hyun Choi, Sergio Bampi
    CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:337-347 [Conf]
    
30. Christophe Lallement, François Pêcheux, Yannick Hervé
    A VHDL-AMS Case Study: The Incremental Design of an Efficient 3^rd Generation MOS Model of a Deep Sub Micron Transistor. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:349-360 [Conf]
    
31. Peer Johannsen, Rolf Drechsler
    Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:361-374 [Conf]
    
32. Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
    Functional Test Generation using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:375-387 [Conf]
    
33. Erik Jan Marinissen
    An Industrial Approach to Core-Based System Chip Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:389-400 [Conf]
    
34. Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre
    Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:401-412 [Conf]
    
35. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Random Adjacent Sequences: An Efficient Solution for Logic BIST. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:413-424 [Conf]
    
36. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
    On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:425-436 [Conf]
    
37. Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski
    Built-in Test of Analog Non-Linear Circuits in a SOC Environment. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:437-448 [Conf]
    
38. B. Casadei, J. P. Le Normand, Y. Hu, B. Cunin
    Design of a Fast CMOS APS Imager for High Speed Laser Detections. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:449-460 [Conf]
    
39. Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
    Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:461-472 [Conf]