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Publications of Author

1. Pramote Kuacharoen, Vincent John Mooney, Vijay K. Madisetti
   Software Streaming via Block Streaming. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10912-10917 [Conf]
   
2. Vincent John Mooney
   Hardware/Software Partitioning of Operating Systems. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10338-10339 [Conf]
   
3. Kyeong Keol Ryu, Vincent John Mooney
   Automated Bus Generation for Multiprocessor SoC Design. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10282-10289 [Conf]
   
4. Pramote Kuacharoen, Tankut Akgul, Vincent John Mooney, Vijay K. Madisetti
   Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems. [Citation Graph (0, 0)][DBLP]
   DSD, 2001, pp:400-407 [Conf]
   
5. Pramote Kuacharoen, Mohamed Shalan, Vincent John Mooney
   A Configurable Hardware Scheduler for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
   Engineering of Reconfigurable Systems and Algorithms, 2003, pp:95-101 [Conf]
   
6. Krishna V. Palem, Rodric M. Rabbah, Vincent John Mooney, Pinar Korkmaz, Kiran Puttaswamy
   Design space optimization of embedded memory systems via data remapping. [Citation Graph (0, 0)][DBLP]
   LCTES-SCOPES, 2002, pp:28-37 [Conf]
   
7. Tankut Akgul, Vincent John Mooney
   Instruction-level reverse execution for debugging. [Citation Graph (0, 0)][DBLP]
   PASTE, 2002, pp:18-25 [Conf]
   
8. Bilge Saglam Akgul, Vincent John Mooney, Henrik Thane, Pramote Kuacharoen
   Hardware Support for Priority Inheritance. [Citation Graph (0, 0)][DBLP]
   RTSS, 2003, pp:246-0 [Conf]
   
9. Yudong Tan, Vincent John Mooney
   Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2004, pp:182-199 [Conf]
   
10. Jaehwan John Lee, Vincent John Mooney
    A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:12, pp:1377-1389 [Journal]
    
11. Se Hun Kim, Vincent John Mooney
    Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:367-372 [Conf]