The SCEAS System
Navigation Menu

Conferences in DBLP

Euromicro Symposium on Digital Systems Design (dsd)
2001 (conf/dsd/2001)

  1. Kjell Torkelsson, Johan Ditmar
    Header Compression in Handel-C - An Internet Application and a New Design Language. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:2-7 [Conf]
  2. George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos
    A Multi-Lingual Synthesis and Verification Environment. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:8-15 [Conf]
  3. Volker Aue, Johannes Kneip, Matthias Weiss, Michael Bolle, Gerhard Fettweis
    A Design Methodology for High Performance IC's: Wireless Broadband Radio Baseband Case Study. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:16-20 [Conf]
  4. Juha-Pekka Soininen, Sandrine Boumard, Tommi Salminen, Hannu Heusala
    Application of Decision-Making Method for Architecture Selection of ADSL Modem. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:21-29 [Conf]
  5. Lech Józwiak, Artur Chojnacki
    Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:30-37 [Conf]
  6. Mariusz Rawski, Rafal Rzechowski, Zbigniew Jachna, Ireneusz Brzozowski
    Practical Aspects of Logic Synthesis Based on Functional Decomposition. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:38-45 [Conf]
  7. Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk
    Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:46-53 [Conf]
  8. Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther
    Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:54-61 [Conf]
  9. Rolf Ernst
    Combining Languages in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:62-0 [Conf]
  10. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Hierarchical Modeling and Verification of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:63-71 [Conf]
  11. Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler
    Minimization of OPKFDDs Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:72-78 [Conf]
  12. Pawel Kerntopf
    An Approach to Minimization of Decision Diagrams . [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:79-86 [Conf]
  13. Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky
    Synthesis of ASM-based Self-Checking Controllers. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:87-93 [Conf]
  14. Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo
    Two-Criterial Constraint-Driven FSM State Encoding for Low Power. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:94-101 [Conf]
  15. Steven A. Guccione
    Reconfigurable Computing at Xilinx. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:102-0 [Conf]
  16. Reiner W. Hartenstein
    Reconfigurable Computing: A New Business Model and its Impact on SoC Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:103-111 [Conf]
  17. Iouliia Skliarova, António de Brito Ferrari
    Design and Implementation of Reconfigurable Processor for Problems of Combinatorial Computations. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:112-119 [Conf]
  18. Claudia Feregrino Uribe, S. R. Jones
    Optimisation of PPMC Model for Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:120-126 [Conf]
  19. Ernesto Martins, José Alberto Fonseca
    Traffic Scheduling Coprocessor with Schedulability Analysis Capability. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:127-134 [Conf]
  20. L. Bubb, Martyn Edwards, Peter Green, C. Pimlott, K. Rees, M. Stewart, A. Taylor, M. Vakondios, J. Yates
    A Run-Time Support Environment for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:135-143 [Conf]
  21. Muthukumar Venkatesan
    An Improved Input-Output Encoding Approach for Functional Decomposition. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:144-147 [Conf]
  22. Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst
    Level Assignment for Displaying Combinational Logic. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:148-151 [Conf]
  23. Wiktor B. Daszczuk, W. Grabski, J. Miescicki, Jacek Wytrebowicz
    System Modeling in the COSMA Environment. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:152-157 [Conf]
  24. Wiktor B. Daszczuk
    Evaluation of Temporal Formulas Based on "Checking by Spheres". [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:158-164 [Conf]
  25. Christian Stangier, Ulrich Holtmann
    Applying Formal Verification with Protocol Compiler. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:165-169 [Conf]
  26. Solovjev Valeri
    Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:170-177 [Conf]
  27. Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur Steven, Lucian N. Vintan
    Dynamic Branch Prediction Using Neural Networks. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:178-185 [Conf]
  28. Colin Egan, Gordon Steven, Won Shim, Lucian N. Vintan
    Applying Caching to Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:186-193 [Conf]
  29. Janusz Sosnowski, Rafal Jurkiewicz, J. Nowicki
    Experimental Evaluation of CPU Performance Features. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:194-201 [Conf]
  30. Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III
    A Comparison of Five Different Multiprocessor SoC Bus Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:202-211 [Conf]
  31. Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss
    A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:212-219 [Conf]
  32. Krzysztof Kuchcinski, Christophe Wolinski
    Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:220-227 [Conf]
  33. Vladimir Hahanov, Anna Babich
    Test Generation and Fault Simulation Methods on the Basis of Cubic Algebra for Digital Devices. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:228-235 [Conf]
  34. Pawel Tomaszewicz, Mariusz Rawski
    Self-Testing of User-Programmed FPGAs Based on the Concept of Linear Segments. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:236-243 [Conf]
  35. Marek A. Perkowski, Pawel Kerntopf
    Fundamentals of Reversible Logic and Computing. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:244-0 [Conf]
  36. Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
    Regular Realization of Symmetric Functions Using Reversible Logic. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:245-253 [Conf]
  37. Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif
    Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:254-261 [Conf]
  38. José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
    FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:262-269 [Conf]
  39. Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido
    Cork Stopper Classification Using FPGAs and Digital Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:270-275 [Conf]
  40. Oswaldo Cadenas, Graham M. Megson
    Pipelining Considerations for an FPGA Case. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:276-285 [Conf]
  41. Agnieszka Konczykowska
    Very High (Over 40 Gb/s) Speed Circuits for Optical Communications - Design Methodolgy and Application Examples. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:286-291 [Conf]
  42. Enrique San Millán, Luis Entrena, José Alberto Espejo
    On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:292-299 [Conf]
  43. Petr Fiser, Jan Hlavicka
    On the Use of Mutations in Boolean Minimization. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:300-309 [Conf]
  44. Andrzej Krasniewski
    Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:310-317 [Conf]
  45. Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng
    Fast Test Cost Calculation for Hybrid BIST in Digital Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:318-325 [Conf]
  46. Simon Leung, Adam Postula, Ahmed Hemani
    Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:326-335 [Conf]
  47. Mark G. Arnold
    Design of a Faithful LNS Interpolator. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:336-345 [Conf]
  48. Chichyang Chen, Liang-An Chen, Jih-Ren Cheng
    Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:346-353 [Conf]
  49. Albert A. Liddicoat, Michael J. Flynn
    High-Performance Floating Point Divide. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:354-363 [Conf]
  50. Andrzej Ryszko, Kazimierz Wiatr
    An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:364-367 [Conf]
  51. G. Coldani, Giovanni Danese, R. Gandolfi, P. Ghidetti, Francesco Leporati, R. Lombardi
    Portable Acquisition System for Measurements of Pressures, Temperatures and Humidity in Lower Limb Prosthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:368-371 [Conf]
  52. F. Lesser, J. de Cuveland, Volker Lindenstruth, C. Reichling, R. Schneider, M. W. Schulz
    A MIMD-Based Multi Threaded Real-Time Processor for Pattern Recognition. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:372-375 [Conf]
  53. Stefan Lund, Lars Bengtsson
    Synchronizing a High-Speed SIMD Processor Array. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:376-381 [Conf]
  54. Aitor Ibarra, Juan Lanchares, José Ignacio Hidalgo, F. Saenz
    Pipelined Genetic Architecture with Fitness on the Fly. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:382-385 [Conf]
  55. Jacek Marczynski, Daniel Tabak
    A Wireless Interconnection Network for Parallel Processing. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:386-389 [Conf]
  56. Juan C. Moure, R. B. García, Dolores Rexachs, Emilio Luque
    Improving Single-Thread Fetch Performance on a Multithreaded Processor. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:390-395 [Conf]
  57. Øyvind Strøm, Einar J. Aas
    An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:396-399 [Conf]
  58. Pramote Kuacharoen, Tankut Akgul, Vincent John Mooney, Vijay K. Madisetti
    Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:400-407 [Conf]
  59. Paul Kartschoke, Stephen Geissler
    Timing Driven Wiring on an Advanced Microprocessor. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:408-413 [Conf]
  60. Daniel Eckerbert, Per Larsson-Edefors
    Interconnect-Driven Short-Circuit Power Modeling. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:414-421 [Conf]
  61. Krzysztof S. Berezowski
    Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:422-429 [Conf]
  62. Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    A Global Routing Technique for Wave-Steering Design Methodology. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:430-437 [Conf]
  63. Mikael M. Nordman, Wojciech E. Kozlowski, Olavi Vähämäki
    Synchronizing Low-Cost Energy Aware Sensors in a Short-range Wireless Cell. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:438-445 [Conf]
  64. Michael C. Miller, Daniel Tabak
    A Multiple Context Reconfigurable Functional Unit. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:446-452 [Conf]
  65. Marek Gorgon, Jaromir Przybylo
    FPGA Based Controller for Heterogeneous Image Processing System. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:453-457 [Conf]
  66. Ernest Jamro, Kazimierz Wiatr
    FPGA Implementation of Addition as a Part of the Convolution. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:458-465 [Conf]
  67. Ernest Jamro, Kazimierz Wiatr
    Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:466-474 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002