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Publications of Author

1. Hwang-Cherng Chow, I-Chyn Wey
   A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:121-124 [Conf]
   
2. I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu
   A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1074-1077 [Conf]
   
3. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
   A scalable DCO design for portable ADPLL designs. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 2005, pp:5449-5452 [Conf]
   
4. Hwang-Cherng Chow, I-Chyn Wey
   A 3.3 V 1 GHz high speed pipelined Booth multiplier. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2002, pp:457-460 [Conf]
   
5. Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao
   Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:1803-1806 [Conf]
   
6. Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu
   Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:869-872 [Conf]
   
7. Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu
   A portable all-digital pulsewidth control loop for SOC applications. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
8. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
   A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
9. 
   An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. [Citation Graph (, )][DBLP]
   
   
10. 
    Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency. [Citation Graph (, )][DBLP]